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Searched refs:bltc (Results 1 – 25 of 25) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/micromips32r6/
Dinvalid.s301 …bltc $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instru…
302 bltc $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different
303 bltc $2, $4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
304 bltc $2, $4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
305 bltc $2, $4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
306 bltc $2, $4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
Dvalid.s35 bltc $3,$4, 16 # CHECK: bltc $3, $4, 16 # encoding: [0xd4,0x83,0x00,0x04]
/external/llvm/test/MC/Disassembler/Mips/mips32r6/
Dvalid-mips32r6-el.txt48 0x40 0x00 0xa6 0x5c # CHECK: bltc $5, $6, 260
49 0xfa 0xff 0xa6 0x5c # CHECK: bltc $5, $6, -20
Dvalid-mips32r6.txt164 0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 260
165 0x5c 0xa6 0xff 0xfa # CHECK: bltc $5, $6, -20
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips32r6/
Dvalid-mips32r6-el.txt49 0x40 0x00 0xa6 0x5c # CHECK: bltc $5, $6, 260
50 0xfa 0xff 0xa6 0x5c # CHECK: bltc $5, $6, -20
Dvalid-mips32r6.txt174 0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 260
175 0x5c 0xa6 0xff 0xfa # CHECK: bltc $5, $6, -20
/external/llvm/test/MC/Disassembler/Mips/mips64r6/
Dvalid-mips64r6-el.txt41 0x40 0x00 0xa6 0x5c # CHECK: bltc $5, $6, 260
42 0xfa 0xff 0xa6 0x5c # CHECK: bltc $5, $6, -20
Dvalid-mips64r6.txt183 0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 260
184 0x5c 0xa6 0xff 0xfa # CHECK: bltc $5, $6, -20
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64r6/
Dvalid-mips64r6-el.txt41 0x40 0x00 0xa6 0x5c # CHECK: bltc $5, $6, 260
42 0xfa 0xff 0xa6 0x5c # CHECK: bltc $5, $6, -20
Dvalid-mips64r6.txt193 0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 260
194 0x5c 0xa6 0xff 0xfa # CHECK: bltc $5, $6, -20
/external/llvm/test/MC/Mips/micromips32r6/
Dvalid.s26 bltc $3,$4, 16 # CHECK: bltc $3, $4, 16 # encoding: [0xc4,0x83,0x00,0x08]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td85 class BLTC64_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR64Opnd>;
DMicroMips32r6InstrInfo.td72 class BLTC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltc", 0b110101>,
333 class BLTC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltc", brtarget_lsl2_mm,
DMips32r6InstrInfo.td439 class BLTC_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR32Opnd>;
/external/v8/src/mips/
Dassembler-mips.h755 void bltc(Register rs, Register rt, int16_t offset);
756 inline void bltc(Register rs, Register rt, Label* L) { in bltc() function
757 bltc(rs, rt, shifted_branch_offset(L)); in bltc()
Dmacro-assembler-mips.cc2967 bltc(scratch, rs, offset); in BranchShortHelperR6()
3004 bltc(rs, scratch, offset); in BranchShortHelperR6()
Dassembler-mips.cc1691 void Assembler::bltc(Register rs, Register rt, int16_t offset) { in bltc() function in v8::internal::Assembler
/external/llvm/test/MC/Disassembler/Mips/micromips32r6/
Dvalid.txt45 0xc4 0x83 0x00 0x08 # CHECK: bltc $3, $4, 16
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/micromips32r6/
Dvalid.txt45 0xd4 0x83 0x00 0x04 # CHECK: bltc $3, $4, 20
/external/v8/src/mips64/
Dassembler-mips64.h765 void bltc(Register rs, Register rt, int16_t offset);
766 inline void bltc(Register rs, Register rt, Label* L) { in bltc() function
767 bltc(rs, rt, shifted_branch_offset(L)); in bltc()
Dmacro-assembler-mips64.cc3465 bltc(scratch, rs, offset); in BranchShortHelperR6()
3502 bltc(rs, scratch, offset); in BranchShortHelperR6()
Dassembler-mips64.cc1671 void Assembler::bltc(Register rs, Register rt, int16_t offset) { in bltc() function in v8::internal::Assembler
/external/llvm/lib/Target/Mips/
DMicroMips32r6InstrInfo.td62 class BLTC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltc", 0b110001>;
284 class BLTC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltc", brtarget_mm,
DMips32r6InstrInfo.td400 class BLTC_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR32Opnd>;
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenAsmMatcher.inc4858 "\005bleul\004blez\007blezalc\005blezc\005blezl\003blt\004bltc\004bltl\004"
5384 …{ 1316 /* bltc */, Mips::BLTC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_Has…
5385 …{ 1316 /* bltc */, Mips::BLTC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Featur…
5386 …{ 1316 /* bltc */, Mips::BLTC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_H…
8322 …{ Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1316 /* bltc */, MCK_GPR32AsmReg, …
8323 …{ Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1316 /* bltc */, MCK_JumpTarget, 4…
8324 { Feature_InMicroMips|Feature_HasMips32r6, 1316 /* bltc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8325 { Feature_InMicroMips|Feature_HasMips32r6, 1316 /* bltc */, MCK_JumpTarget, 4 /* 2 */ },
8326 …{ Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1316 /* bltc */, MCK_GPR64AsmReg, 3 /* …
8327 …{ Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1316 /* bltc */, MCK_JumpTarget, 4 /* 2…