Searched refs:bnezc (Results 1 – 25 of 64) sorted by relevance
123
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/compactbranches/ |
| D | no-beqzc-bnezc.ll | 8 ; bnezc and beqzc have restriction that $rt != 0
12 ; CHECK-NOT: bnezc $0
59 ; CHECK-NOT: bnezc $0
120 ; CHECK: bnezc ${{[0-9]+}}, $BB
|
| D | unsafe-in-forbidden-slot.ll | 27 ; CHECK: bnezc
|
| /external/llvm/test/CodeGen/Mips/compactbranches/ |
| D | no-beqzc-bnezc.ll | 5 ; bnezc and beqzc have restriction that $rt != 0
9 ; CHECK-NOT: bnezc $0
|
| D | beqc-bnec-register-constraint.ll | 4 ; Cases where $rs == 0 and $rt != 0 should be transformed into beqzc/bnezc.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/longbranch/ |
| D | compact-branches-long-branch.ll | 13 ; CHECK: bnezc
93 ; CHECK: bnezc
125 ; CHECK: bnezc
|
| /external/llvm/test/MC/Mips/micromips32r6/ |
| D | relocations.s | 23 # CHECK-FIXUP: bnezc $3, bar # encoding: [0xa0,0b011AAAAA,A,A]
43 bnezc $3, bar
|
| /external/llvm/test/CodeGen/Mips/ |
| D | fpbr.ll | 22 ; 64-GPR: bnezc $[[GPRCC]], $BB0_2
56 ; 64-GPR: bnezc $[[GPRCC]], $BB1_2
117 ; 64-GPR: bnezc $[[GPRCC]], $BB3_2
147 ; 64-GPR: bnezc $[[GPRCC]], $BB4_2
|
| D | micromips-compact-branches.ll | 19 ; CHECK: bnezc
|
| D | analyzebranch.ll | 22 ; GPR: bnezc $[[GPRCC]], $BB
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/micromips32r6/ |
| D | relocations.s | 26 # CHECK-FIXUP: bnezc $3, bar # encoding: [0xa0,0b011AAAAA,A,A]
48 bnezc $3, bar
|
| D | invalid.s | 356 …bnezc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instru…
357 bnezc $2, -4194308 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
358 bnezc $2, -4194303 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
359 bnezc $2, 4194304 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
360 bnezc $2, 4194303 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| D | relocations.s | 26 # CHECK-FIXUP: bnezc $3, bar # encoding: [0xa0,0b011AAAAA,A,A]
48 bnezc $3, bar
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
| D | branch-relaxation-with-hazard.ll | 20 ; CHECK-PIC: bnezc
26 ; CHECK-STATIC: bnezc
|
| D | fpbr.ll | 23 ; 64-GPR: bnezc $[[GPRCC]], .LBB0_2
58 ; 64-GPR: bnezc $[[GPRCC]], .LBB1_2
121 ; 64-GPR: bnezc $[[GPRCC]], .LBB3_2
152 ; 64-GPR: bnezc $[[GPRCC]], .LBB4_2
|
| D | micromips-compact-branches.ll | 19 ; CHECK: bnezc
|
| D | longbranch.ll | 118 ; O32-R6-STATIC-NEXT: bnezc $4, $BB0_2
232 ; MICROMIPSSTATIC-NEXT: bnezc $4, $BB0_2
245 ; MICROMIPSR6STATIC-NEXT: bnezc $4, $BB0_2
260 ; MICROMIPSR6PIC-NEXT: bnezc $4, $BB0_3
|
| D | analyzebranch.ll | 60 ; MIPS32r6-NEXT: bnezc $1, $BB0_2
67 ; MIPS32r6-NEXT: bnezc $1, $BB0_3
141 ; MIPS64R6-NEXT: bnezc $1, .LBB0_3
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r6/ |
| D | relocations.s | 20 # CHECK-FIXUP: bnezc $9, bar # encoding: [0xf9,0b001AAAAA,A,A]
68 bnezc $9, bar
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| D | relocations.s | 20 # CHECK-FIXUP: bnezc $9, bar # encoding: [0xf9,0b001AAAAA,A,A]
64 bnezc $9, bar
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| D | relocations.s | 20 # CHECK-FIXUP: bnezc $9, bar # encoding: [0xf9,0b001AAAAA,A,A]
69 bnezc $9, bar
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r6/ |
| D | relocations.s | 20 # CHECK-FIXUP: bnezc $9, bar # encoding: [0xf9,0b001AAAAA,A,A]
73 bnezc $9, bar
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/ExecutionEngine/RuntimeDyld/Mips/ |
| D | ELF_O32R6_relocations.s | 33 bnezc $5,foo
|
| D | ELF_N64R6_relocations.s | 38 bnezc $5,foo
|
| /external/llvm/test/ExecutionEngine/RuntimeDyld/Mips/ |
| D | ELF_N64R6_relocations.s | 37 bnezc $5,foo
|
| D | ELF_O32R6_relocations.s | 32 bnezc $5,foo
|
123