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Searched refs:bsel (Results 1 – 25 of 36) sorted by relevance

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/external/u-boot/arch/arm/mach-socfpga/
Dmisc_gen5.c142 const u32 bsel = in print_cpuinfo() local
148 printf("BOOT: %s\n", bsel_str[bsel].name); in print_cpuinfo()
156 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; in arch_misc_init() local
158 env_set("bootmode", bsel_str[bsel].mode); in arch_misc_init()
Dspl.c45 const u32 bsel = readl(&sysmgr_regs->bootinfo); in spl_boot_device() local
47 switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) { in spl_boot_device()
64 printf("Invalid boot device (bsel=%08x)!\n", bsel); in spl_boot_device()
Dmisc_arria10.c249 const u32 bsel = in print_cpuinfo() local
254 printf("BOOT: %s\n", bsel_str[bsel].name); in print_cpuinfo()
Dmisc.c30 struct bsel bsel_str[] = {
/external/u-boot/arch/arm/mach-socfpga/include/mach/
Dmisc.h11 struct bsel { struct
16 extern struct bsel bsel_str[]; argument
Dsystem_manager.h92 #define SYSMGR_GET_BOOTINFO_BSEL(bsel) \ argument
93 (((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7)
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/msa/
Dtest_vec.s6 # CHECK: bsel.v $w8, $w0, $w14 # encoding: [0x78,0xce,0x02,0x1e]
14 bsel.v $w8, $w0, $w14
/external/llvm/test/MC/Mips/msa/
Dtest_vec.s6 # CHECK: bsel.v $w8, $w0, $w14 # encoding: [0x78,0xce,0x02,0x1e]
14 bsel.v $w8, $w0, $w14
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMSA.txt60 Furthermore, the compiler may use bsel.[bhwd] for some masks that do
63 bmnz.v, bmz.v, bsel.v:
66 It is (currently) not possible to emit bmz.v, or bsel.v since bmnz.v is
74 bsel.v wd, ws, wt/i8 -> (vselect wd, wt/i8, ws)
/external/llvm/lib/Target/Mips/
DMSA.txt60 Furthermore, the compiler may use bsel.[bhwd] for some masks that do
63 bmnz.v, bmz.v, bsel.v:
66 It is (currently) not possible to emit bmz.v, or bsel.v since bmnz.v is
74 bsel.v wd, ws, wt/i8 -> (vselect wd, wt/i8, ws)
/external/capstone/suite/MC/Mips/
Dtest_vec.s.cs5 0x78,0xce,0x02,0x1e = bsel.v $w8, $w0, $w14
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/msa/
Dtest_vec.txt6 0x78 0xce 0x02 0x1e # CHECK: bsel.v $w8, $w0, $w14
/external/llvm/test/MC/Disassembler/Mips/msa/
Dtest_vec.txt6 0x78 0xce 0x02 0x1e # CHECK: bsel.v $w8, $w0, $w14
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dbfi.ll146 %bsel = select i1 %bcmp, i32 %bor, i32 %asel
148 ret i32 %bsel
/external/llvm/test/CodeGen/ARM/
Dbfi.ll146 %bsel = select i1 %bcmp, i32 %bor, i32 %asel
148 ret i32 %bsel
/external/llvm/test/CodeGen/Mips/msa/
Dvec.ll421 %6 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %3, <16 x i8> %4, <16 x i8> %5)
434 ; bmnz.v is the same as bsel.v with (wd_in, wt, ws) -> (wt, ws, wd_in)
452 %6 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %3, <16 x i8> %4, <16 x i8> %5)
465 ; bmnz.v is the same as bsel.v with (wd_in, wt, ws) -> (wt, ws, wd_in)
483 %6 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %3, <16 x i8> %4, <16 x i8> %5)
496 ; bmnz.v is the same as bsel.v with (wd_in, wt, ws) -> (wt, ws, wd_in)
514 %6 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %3, <16 x i8> %4, <16 x i8> %5)
527 ; bmnz.v is the same as bsel.v with (wd_in, wt, ws) -> (wt, ws, wd_in)
943 declare <16 x i8> @llvm.mips.bsel.v(<16 x i8>, <16 x i8>, <16 x i8>) nounwind
Dcompare_float.ll529 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]]
551 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]]
571 ; CHECK-DAG: bsel.v [[R4]], [[R3:\$w[0-9]+]], [[R1]]
591 ; CHECK-DAG: bsel.v [[R4]], [[R3:\$w[0-9]+]], [[R1]]
Dcompare.ll765 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]]
787 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]]
809 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]]
853 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]]
875 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]]
897 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]]
936 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
956 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
976 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
1015 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
[all …]
Dbitwise.ll1040 ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]]
1059 ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]]
1078 ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/
Dvec.ll421 %6 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %3, <16 x i8> %4, <16 x i8> %5)
434 ; bmnz.v is the same as bsel.v with (wd_in, wt, ws) -> (wt, ws, wd_in)
452 %6 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %3, <16 x i8> %4, <16 x i8> %5)
465 ; bmnz.v is the same as bsel.v with (wd_in, wt, ws) -> (wt, ws, wd_in)
483 %6 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %3, <16 x i8> %4, <16 x i8> %5)
496 ; bmnz.v is the same as bsel.v with (wd_in, wt, ws) -> (wt, ws, wd_in)
514 %6 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %3, <16 x i8> %4, <16 x i8> %5)
527 ; bmnz.v is the same as bsel.v with (wd_in, wt, ws) -> (wt, ws, wd_in)
943 declare <16 x i8> @llvm.mips.bsel.v(<16 x i8>, <16 x i8>, <16 x i8>) nounwind
Dcompare_float.ll529 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]]
551 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]]
571 ; CHECK-DAG: bsel.v [[R4]], [[R3:\$w[0-9]+]], [[R1]]
591 ; CHECK-DAG: bsel.v [[R4]], [[R3:\$w[0-9]+]], [[R1]]
Dcompare.ll765 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]]
787 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]]
809 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]]
853 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]]
875 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]]
897 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]]
936 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
956 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
976 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
1015 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
[all …]
Dbitwise.ll1040 ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]]
1059 ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]]
1078 ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r2/
Dinvalid-msa.s11 …bsel.v $w28,$w7,$w0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
/external/llvm/test/MC/Mips/mips32r2/
Dinvalid-msa.s11 …bsel.v $w28,$w7,$w0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…

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