1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 */
5
6 #include <common.h>
7 #include <asm/io.h>
8 #include <asm/pl310.h>
9 #include <asm/u-boot.h>
10 #include <asm/utils.h>
11 #include <image.h>
12 #include <asm/arch/reset_manager.h>
13 #include <spl.h>
14 #include <asm/arch/system_manager.h>
15 #include <asm/arch/freeze_controller.h>
16 #include <asm/arch/clock_manager.h>
17 #include <asm/arch/misc.h>
18 #include <asm/arch/scan_manager.h>
19 #include <asm/arch/sdram.h>
20 #include <asm/arch/scu.h>
21 #include <asm/arch/nic301.h>
22 #include <asm/sections.h>
23 #include <fdtdec.h>
24 #include <watchdog.h>
25 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
26 #include <asm/arch/pinmux.h>
27 #endif
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
32 static struct pl310_regs *const pl310 =
33 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
34 static struct scu_registers *scu_regs =
35 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
36 static struct nic301_registers *nic301_regs =
37 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
38 #endif
39
40 static const struct socfpga_system_manager *sysmgr_regs =
41 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
42
spl_boot_device(void)43 u32 spl_boot_device(void)
44 {
45 const u32 bsel = readl(&sysmgr_regs->bootinfo);
46
47 switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
48 case 0x1: /* FPGA (HPS2FPGA Bridge) */
49 return BOOT_DEVICE_RAM;
50 case 0x2: /* NAND Flash (1.8V) */
51 case 0x3: /* NAND Flash (3.0V) */
52 socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
53 return BOOT_DEVICE_NAND;
54 case 0x4: /* SD/MMC External Transceiver (1.8V) */
55 case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
56 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
57 socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
58 return BOOT_DEVICE_MMC1;
59 case 0x6: /* QSPI Flash (1.8V) */
60 case 0x7: /* QSPI Flash (3.0V) */
61 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
62 return BOOT_DEVICE_SPI;
63 default:
64 printf("Invalid boot device (bsel=%08x)!\n", bsel);
65 hang();
66 }
67 }
68
69 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
socfpga_nic301_slave_ns(void)70 static void socfpga_nic301_slave_ns(void)
71 {
72 writel(0x1, &nic301_regs->lwhps2fpgaregs);
73 writel(0x1, &nic301_regs->hps2fpgaregs);
74 writel(0x1, &nic301_regs->acp);
75 writel(0x1, &nic301_regs->rom);
76 writel(0x1, &nic301_regs->ocram);
77 writel(0x1, &nic301_regs->sdrdata);
78 }
79
board_init_f(ulong dummy)80 void board_init_f(ulong dummy)
81 {
82 const struct cm_config *cm_default_cfg = cm_get_default_config();
83 unsigned long sdram_size;
84 unsigned long reg;
85
86 /*
87 * First C code to run. Clear fake OCRAM ECC first as SBE
88 * and DBE might triggered during power on
89 */
90 reg = readl(&sysmgr_regs->eccgrp_ocram);
91 if (reg & SYSMGR_ECC_OCRAM_SERR)
92 writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
93 &sysmgr_regs->eccgrp_ocram);
94 if (reg & SYSMGR_ECC_OCRAM_DERR)
95 writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN,
96 &sysmgr_regs->eccgrp_ocram);
97
98 memset(__bss_start, 0, __bss_end - __bss_start);
99
100 socfpga_nic301_slave_ns();
101
102 /* Configure ARM MPU SNSAC register. */
103 setbits_le32(&scu_regs->sacr, 0xfff);
104
105 /* Remap SDRAM to 0x0 */
106 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
107 writel(0x1, &pl310->pl310_addr_filter_start);
108
109 debug("Freezing all I/O banks\n");
110 /* freeze all IO banks */
111 sys_mgr_frzctrl_freeze_req();
112
113 /* Put everything into reset but L4WD0. */
114 socfpga_per_reset_all();
115 /* Put FPGA bridges into reset too. */
116 socfpga_bridges_reset(1);
117
118 socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
119 socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
120 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
121
122 timer_init();
123
124 debug("Reconfigure Clock Manager\n");
125 /* reconfigure the PLLs */
126 if (cm_basic_init(cm_default_cfg))
127 hang();
128
129 /* Enable bootrom to configure IOs. */
130 sysmgr_config_warmrstcfgio(1);
131
132 /* configure the IOCSR / IO buffer settings */
133 if (scan_mgr_configure_iocsr())
134 hang();
135
136 sysmgr_config_warmrstcfgio(0);
137
138 /* configure the pin muxing through system manager */
139 sysmgr_config_warmrstcfgio(1);
140 sysmgr_pinmux_init();
141 sysmgr_config_warmrstcfgio(0);
142
143 /* De-assert reset for peripherals and bridges based on handoff */
144 reset_deassert_peripherals_handoff();
145 socfpga_bridges_reset(0);
146
147 debug("Unfreezing/Thaw all I/O banks\n");
148 /* unfreeze / thaw all IO banks */
149 sys_mgr_frzctrl_thaw_req();
150
151 /* enable console uart printing */
152 preloader_console_init();
153
154 if (sdram_mmr_init_full(0xffffffff) != 0) {
155 puts("SDRAM init failed.\n");
156 hang();
157 }
158
159 debug("SDRAM: Calibrating PHY\n");
160 /* SDRAM calibration */
161 if (sdram_calibration_full() == 0) {
162 puts("SDRAM calibration failed.\n");
163 hang();
164 }
165
166 sdram_size = sdram_calculate_size();
167 debug("SDRAM: %ld MiB\n", sdram_size >> 20);
168
169 /* Sanity check ensure correct SDRAM size specified */
170 if (get_ram_size(0, sdram_size) != sdram_size) {
171 puts("SDRAM size check failed!\n");
172 hang();
173 }
174
175 socfpga_bridges_reset(1);
176
177 /* Configure simple malloc base pointer into RAM. */
178 gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
179 }
180 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
spl_board_init(void)181 void spl_board_init(void)
182 {
183 /* configuring the clock based on handoff */
184 cm_basic_init(gd->fdt_blob);
185 WATCHDOG_RESET();
186
187 config_dedicated_pins(gd->fdt_blob);
188 WATCHDOG_RESET();
189
190 /* Release UART from reset */
191 socfpga_reset_uart(0);
192
193 /* enable console uart printing */
194 preloader_console_init();
195
196 WATCHDOG_RESET();
197
198 /* Add device descriptor to FPGA device table */
199 socfpga_fpga_add();
200 }
201
board_init_f(ulong dummy)202 void board_init_f(ulong dummy)
203 {
204 /*
205 * Configure Clock Manager to use intosc clock instead external osc to
206 * ensure success watchdog operation. We do it as early as possible.
207 */
208 cm_use_intosc();
209
210 socfpga_watchdog_disable();
211
212 arch_early_init_r();
213
214 #ifdef CONFIG_HW_WATCHDOG
215 /* release osc1 watchdog timer 0 from reset */
216 socfpga_reset_deassert_osc1wd0();
217
218 /* reconfigure and enable the watchdog */
219 hw_watchdog_init();
220 WATCHDOG_RESET();
221 #endif /* CONFIG_HW_WATCHDOG */
222 }
223 #endif
224