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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AVR/
Dinst-family-set-clr-flag.s8 bset 0 label
12 bset 1 label
16 bset 2 label
20 bset 3 label
24 bset 4 label
28 bset 5 label
32 bset 6 label
36 bset 7 label
/external/mesa3d/src/gallium/drivers/virgl/
Dvirgl_screen.c73 return vscreen->caps.caps.v1.bset.occlusion_query; in virgl_get_param()
75 return vscreen->caps.caps.v1.bset.mirror_clamp; in virgl_get_param()
87 return vscreen->caps.caps.v1.bset.indep_blend_enable; in virgl_get_param()
89 return vscreen->caps.caps.v1.bset.indep_blend_func; in virgl_get_param()
94 return vscreen->caps.caps.v1.bset.fragment_coord_conventions; in virgl_get_param()
96 return vscreen->caps.caps.v1.bset.depth_clip_disable; in virgl_get_param()
103 return vscreen->caps.caps.v1.bset.primitive_restart; in virgl_get_param()
105 return vscreen->caps.caps.v1.bset.shader_stencil_export; in virgl_get_param()
110 return vscreen->caps.caps.v1.bset.seamless_cube_map; in virgl_get_param()
112 return vscreen->caps.caps.v1.bset.seamless_cube_map_per_texture; in virgl_get_param()
[all …]
Dvirgl_hw.h248 struct virgl_caps_bool_set1 bset; member
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/
Dshift_no_and.ll166 %2 = tail call <16 x i8> @llvm.mips.bset.b(<16 x i8> %0, <16 x i8> %1)
171 declare <16 x i8> @llvm.mips.bset.b(<16 x i8>, <16 x i8>) nounwind
175 ; CHECK: bset.b
185 %2 = tail call <8 x i16> @llvm.mips.bset.h(<8 x i16> %0, <8 x i16> %1)
190 declare <8 x i16> @llvm.mips.bset.h(<8 x i16>, <8 x i16>) nounwind
194 ; CHECK: bset.h
204 %2 = tail call <4 x i32> @llvm.mips.bset.w(<4 x i32> %0, <4 x i32> %1)
209 declare <4 x i32> @llvm.mips.bset.w(<4 x i32>, <4 x i32>) nounwind
213 ; CHECK: bset.w
223 %2 = tail call <2 x i64> @llvm.mips.bset.d(<2 x i64> %0, <2 x i64> %1)
[all …]
D3r-b.ll415 %2 = tail call <16 x i8> @llvm.mips.bset.b(<16 x i8> %0, <16 x i8> %1)
420 declare <16 x i8> @llvm.mips.bset.b(<16 x i8>, <16 x i8>) nounwind
425 ; CHECK: bset.b
437 %2 = tail call <8 x i16> @llvm.mips.bset.h(<8 x i16> %0, <8 x i16> %1)
442 declare <8 x i16> @llvm.mips.bset.h(<8 x i16>, <8 x i16>) nounwind
447 ; CHECK: bset.h
459 %2 = tail call <4 x i32> @llvm.mips.bset.w(<4 x i32> %0, <4 x i32> %1)
464 declare <4 x i32> @llvm.mips.bset.w(<4 x i32>, <4 x i32>) nounwind
469 ; CHECK: bset.w
481 %2 = tail call <2 x i64> @llvm.mips.bset.d(<2 x i64> %0, <2 x i64> %1)
[all …]
Dshift_constant_pool.ll69 …%0 = tail call <4 x i32> @llvm.mips.bset.w(<4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 …
74 declare <4 x i32> @llvm.mips.bset.w(<4 x i32>, <4 x i32>) nounwind
Dbitwise.ll1329 ; CHECK-DAG: bset.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1346 ; CHECK-DAG: bset.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1363 ; CHECK-DAG: bset.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1380 ; CHECK-DAG: bset.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
/external/llvm/test/CodeGen/Mips/msa/
D3r-b.ll415 %2 = tail call <16 x i8> @llvm.mips.bset.b(<16 x i8> %0, <16 x i8> %1)
420 declare <16 x i8> @llvm.mips.bset.b(<16 x i8>, <16 x i8>) nounwind
425 ; CHECK: bset.b
437 %2 = tail call <8 x i16> @llvm.mips.bset.h(<8 x i16> %0, <8 x i16> %1)
442 declare <8 x i16> @llvm.mips.bset.h(<8 x i16>, <8 x i16>) nounwind
447 ; CHECK: bset.h
459 %2 = tail call <4 x i32> @llvm.mips.bset.w(<4 x i32> %0, <4 x i32> %1)
464 declare <4 x i32> @llvm.mips.bset.w(<4 x i32>, <4 x i32>) nounwind
469 ; CHECK: bset.w
481 %2 = tail call <2 x i64> @llvm.mips.bset.d(<2 x i64> %0, <2 x i64> %1)
[all …]
Dbitwise.ll1329 ; CHECK-DAG: bset.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1346 ; CHECK-DAG: bset.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1363 ; CHECK-DAG: bset.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1380 ; CHECK-DAG: bset.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
/external/capstone/suite/MC/Mips/
Dtest_3r.s.cs62 0x7a,0x1f,0x2f,0xcd = bset.b $w31, $w5, $w31
63 0x7a,0x26,0x63,0x8d = bset.h $w14, $w12, $w6
64 0x7a,0x4c,0x4f,0xcd = bset.w $w31, $w9, $w12
65 0x7a,0x65,0xb1,0x4d = bset.d $w5, $w22, $w5
/external/u-boot/arch/arc/lib/
Dstart.S43 bset r5, r5, 0 ; Disable (+Inv)
/external/llvm/test/MC/Mips/msa/
Dtest_3r.s63 # CHECK: bset.b $w31, $w5, $w31 # encoding: [0x7a,0x1f,0x2f,0xcd]
64 # CHECK: bset.h $w14, $w12, $w6 # encoding: [0x7a,0x26,0x63,0x8d]
65 # CHECK: bset.w $w31, $w9, $w12 # encoding: [0x7a,0x4c,0x4f,0xcd]
66 # CHECK: bset.d $w5, $w22, $w5 # encoding: [0x7a,0x65,0xb1,0x4d]
306 bset.b $w31, $w5, $w31
307 bset.h $w14, $w12, $w6
308 bset.w $w31, $w9, $w12
309 bset.d $w5, $w22, $w5
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/msa/
Dtest_3r.s63 # CHECK: bset.b $w31, $w5, $w31 # encoding: [0x7a,0x1f,0x2f,0xcd]
64 # CHECK: bset.h $w14, $w12, $w6 # encoding: [0x7a,0x26,0x63,0x8d]
65 # CHECK: bset.w $w31, $w9, $w12 # encoding: [0x7a,0x4c,0x4f,0xcd]
66 # CHECK: bset.d $w5, $w22, $w5 # encoding: [0x7a,0x65,0xb1,0x4d]
306 bset.b $w31, $w5, $w31
307 bset.h $w14, $w12, $w6
308 bset.w $w31, $w9, $w12
309 bset.d $w5, $w22, $w5
/external/virglrenderer/src/
Dvrend_renderer.c7862 caps->v1.bset.occlusion_query = 1; in vrend_renderer_fill_caps_v1()
7871 caps->v1.bset.poly_stipple = 1; in vrend_renderer_fill_caps_v1()
7872 caps->v1.bset.color_clamping = 1; in vrend_renderer_fill_caps_v1()
7896 caps->v1.bset.conditional_render = 1; in vrend_renderer_fill_caps_v1()
7899 caps->v1.bset.indep_blend_enable = 1; in vrend_renderer_fill_caps_v1()
7902 caps->v1.bset.instanceid = 1; in vrend_renderer_fill_caps_v1()
7911 caps->v1.bset.fragment_coord_conventions = 1; in vrend_renderer_fill_caps_v1()
7912 caps->v1.bset.depth_clip_disable = 1; in vrend_renderer_fill_caps_v1()
7913 caps->v1.bset.seamless_cube_map = 1; in vrend_renderer_fill_caps_v1()
7916 caps->v1.bset.fragment_coord_conventions = 1; in vrend_renderer_fill_caps_v1()
[all …]
Dvirgl_hw.h297 struct virgl_caps_bool_set1 bset; member
/external/minigbm/
Dvirgl_hw.h248 struct virgl_caps_bool_set1 bset; member
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Sparc/
Dsparc-synthetic-instructions.s90 bset %g1, %g2
92 bset 4, %g2
/external/llvm/test/MC/Sparc/
Dsparc-synthetic-instructions.s90 bset %g1, %g2
92 bset 4, %g2
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/msa/
Dtest_3r.txt63 0x7a 0x1f 0x2f 0xcd # CHECK: bset.b $w31, $w5, $w31
64 0x7a 0x26 0x63 0x8d # CHECK: bset.h $w14, $w12, $w6
65 0x7a 0x4c 0x4f 0xcd # CHECK: bset.w $w31, $w9, $w12
66 0x7a 0x65 0xb1 0x4d # CHECK: bset.d $w5, $w22, $w5
/external/llvm/test/MC/Disassembler/Mips/msa/
Dtest_3r.txt63 0x7a 0x1f 0x2f 0xcd # CHECK: bset.b $w31, $w5, $w31
64 0x7a 0x26 0x63 0x8d # CHECK: bset.h $w14, $w12, $w6
65 0x7a 0x4c 0x4f 0xcd # CHECK: bset.w $w31, $w9, $w12
66 0x7a 0x65 0xb1 0x4d # CHECK: bset.d $w5, $w22, $w5
/external/kernel-headers/original/uapi/linux/
Dbcache.h351 struct bset { struct
/external/virglrenderer/tests/
Dtestvirgl.c303 multisample = v1->bset.texture_multisample; in testvirgl_get_multisample_from_caps()
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td414 // bset reg_or_imm, rd -> or rd,reg_or_imm,rd
415 def : InstAlias<"bset $rs2, $rd", (ORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
416 def : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td414 // bset reg_or_imm, rd -> or rd,reg_or_imm,rd
415 def : InstAlias<"bset $rs2, $rd", (ORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
416 def : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
/external/icu/icu4c/source/i18n/
DdecNumber.cpp5651 decContext aset, bset; /* working contexts */ local
5772 bset=aset;
5773 bset.emax=DEC_MAX_MATH*2; /* use double bounds for the */
5774 bset.emin=-DEC_MAX_MATH*2; /* adjustment calculation */
5782 bset.digits=pp+rhs->digits; /* wider context */
5794 decExpOp(b, a, &bset, &ignore); /* b=exp(-a) */
5797 decMultiplyOp(b, b, rhs, &bset, &ignore); /* b=b*rhs */
5798 decAddOp(b, b, &numone, &bset, DECNEG, &ignore); /* b=b-1 */
5828 bset.digits=pp+rhs->digits; /* wider context */

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