| /external/u-boot/drivers/serial/ |
| D | serial_uniphier.c | 97 unsigned int clk_rate; member
101 { .compatible = "socionext,uniphier-ld4", .clk_rate = 36864000 },
102 { .compatible = "socionext,uniphier-pro4", .clk_rate = 73728000 },
103 { .compatible = "socionext,uniphier-sld8", .clk_rate = 80000000 },
104 { .compatible = "socionext,uniphier-pro5", .clk_rate = 73728000 },
105 { .compatible = "socionext,uniphier-pxs2", .clk_rate = 88888888 },
106 { .compatible = "socionext,uniphier-ld6b", .clk_rate = 88888888 },
107 { .compatible = "socionext,uniphier-ld11", .clk_rate = 58823529 },
108 { .compatible = "socionext,uniphier-ld20", .clk_rate = 58823529 },
109 { .compatible = "socionext,uniphier-pxs3", .clk_rate = 58823529 },
[all …]
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| D | atmel_usart.c | 225 ulong clk_rate; in atmel_serial_enable_clk() local
238 clk_rate = clk_get_rate(&clk); in atmel_serial_enable_clk()
239 if (!clk_rate) in atmel_serial_enable_clk()
242 priv->usart_clk_rate = clk_rate; in atmel_serial_enable_clk()
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| D | serial_msm.c | 156 uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), in msm_uart_clk_init() local
182 ret = clk_set_rate(&clk, clk_rate); in msm_uart_clk_init()
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| /external/u-boot/drivers/phy/ |
| D | phy-stm32-usbphyc.c | 64 void stm32_usbphyc_get_pll_params(u32 clk_rate, struct pll_params *pll_params) in stm32_usbphyc_get_pll_params() argument
80 do_div(ndiv, (clk_rate * 2)); in stm32_usbphyc_get_pll_params()
84 do_div(frac, (clk_rate * 2)); in stm32_usbphyc_get_pll_params()
92 u32 clk_rate = clk_get_rate(&usbphyc->clk); in stm32_usbphyc_pll_init() local
95 if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) { in stm32_usbphyc_pll_init()
97 __func__, clk_rate); in stm32_usbphyc_pll_init()
101 stm32_usbphyc_get_pll_params(clk_rate, &pll_params); in stm32_usbphyc_pll_init()
115 clk_rate, pll_params.ndiv, pll_params.frac); in stm32_usbphyc_pll_init()
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| /external/u-boot/drivers/timer/ |
| D | atmel_pit_timer.c | 44 ulong clk_rate; in atmel_pit_probe() local
51 clk_rate = clk_get_rate(&clk); in atmel_pit_probe()
52 if (!clk_rate) in atmel_pit_probe()
55 uc_priv->clock_rate = clk_rate / 16; in atmel_pit_probe()
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| /external/u-boot/drivers/clk/at91/ |
| D | clk-plladiv.c | 24 ulong clk_rate; in at91_plladiv_clk_get_rate() local
31 clk_rate = clk_get_rate(&source); in at91_plladiv_clk_get_rate()
33 clk_rate /= 2; in at91_plladiv_clk_get_rate()
35 return clk_rate; in at91_plladiv_clk_get_rate()
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| D | clk-peripheral.c | 84 ulong clk_rate; in periph_get_rate() local
93 clk_rate = clk_get_rate(&clk_dev); in periph_get_rate()
97 return clk_rate; in periph_get_rate()
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| D | clk-utmi.c | 27 ulong clk_rate; in utmi_clk_enable() local
44 clk_rate = clk_get_rate(&clk_dev); in utmi_clk_enable()
45 switch (clk_rate) { in utmi_clk_enable()
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| D | clk-generated.c | 53 ulong clk_rate; in generic_clk_get_rate() local
69 clk_rate = clk_get_rate(&parent) / (gckdiv + 1); in generic_clk_get_rate()
73 return clk_rate; in generic_clk_get_rate()
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| /external/u-boot/drivers/adc/ |
| D | rockchip-saradc.c | 32 unsigned long clk_rate; member
109 ret = clk_set_rate(&clk, priv->data->clk_rate); in rockchip_saradc_probe()
149 .clk_rate = 1000000,
155 .clk_rate = 50000,
161 .clk_rate = 1000000,
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| /external/perfetto/src/traced/probes/ftrace/test/data/android_seed_N2F62_3.10.49/events/mdss/mdp_commit/ |
| D | format | 11 field:u32 clk_rate; offset:16; size:4; signed:0;
14 …t fmt: "num=%d play_cnt=%d bandwidth=%llu clk_rate=%u", REC->num, REC->play_cnt, REC->bandwidth, R…
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| /external/perfetto/src/traced/probes/ftrace/test/data/android_walleye_OPM5.171019.017.A1_4.4.88/events/mdss/mdp_commit/ |
| D | format | 11 field:u32 clk_rate; offset:16; size:4; signed:0;
14 …t fmt: "num=%d play_cnt=%d bandwidth=%llu clk_rate=%u", REC->num, REC->play_cnt, REC->bandwidth, R…
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| /external/u-boot/drivers/video/ |
| D | atmel_hlcdfb.c | 258 ulong clk_rate; member
265 ulong clk_rate; in at91_hlcdc_enable_clk() local
276 clk_rate = clk_get_rate(&clk); in at91_hlcdc_enable_clk()
277 if (!clk_rate) { in at91_hlcdc_enable_clk()
282 priv->clk_rate = clk_rate; in at91_hlcdc_enable_clk()
325 value = priv->clk_rate / timing->pixelclock.typ; in atmel_hlcdc_init()
326 if (priv->clk_rate % timing->pixelclock.typ) in atmel_hlcdc_init()
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| /external/u-boot/drivers/i2c/ |
| D | meson_i2c.c | 225 ulong clk_rate; in meson_i2c_set_bus_speed() local
228 clk_rate = clk_get_rate(&i2c->clk); in meson_i2c_set_bus_speed()
229 if (IS_ERR_VALUE(clk_rate)) in meson_i2c_set_bus_speed()
232 div = DIV_ROUND_UP(clk_rate, speed * 4); in meson_i2c_set_bus_speed()
246 debug("meson i2c: set clk %u, src %lu, div %u\n", speed, clk_rate, div); in meson_i2c_set_bus_speed()
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| D | at91_i2c.c | 181 ulong clk_rate; in at91_i2c_enable_clk() local
192 clk_rate = clk_get_rate(&clk); in at91_i2c_enable_clk()
193 if (!clk_rate) in at91_i2c_enable_clk()
196 bus->bus_clk_rate = clk_rate; in at91_i2c_enable_clk()
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| /external/u-boot/drivers/watchdog/ |
| D | armada-37xx-wdt.c | 20 ulong clk_rate; member
106 priv->timeout = ms * priv->clk_rate / 1000 / CNTR_CTRL_PRESCALE_MIN; in a37xx_wdt_start()
140 priv->clk_rate = (ulong)get_ref_clk() * 1000000; in a37xx_wdt_probe()
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| /external/u-boot/drivers/spi/ |
| D | atmel_spi.c | 443 ulong clk_rate; in atmel_spi_enable_clk() local
454 clk_rate = clk_get_rate(&clk); in atmel_spi_enable_clk()
455 if (!clk_rate) in atmel_spi_enable_clk()
458 priv->bus_clk_rate = clk_rate; in atmel_spi_enable_clk()
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| D | atcspi200_spi.c | 345 ulong clk_rate; in atcspi200_spi_get_clk() local
352 clk_rate = clk_get_rate(&clk); in atcspi200_spi_get_clk()
353 if (!clk_rate) in atcspi200_spi_get_clk()
356 ns->clock = clk_rate; in atcspi200_spi_get_clk()
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| D | bcm63xx_hsspi.c | 98 ulong clk_rate; member
145 set = DIV_ROUND_UP(priv->clk_rate, priv->speed); in bcm63xx_hsspi_activate_cs()
364 priv->clk_rate = clk_get_rate(&clk); in bcm63xx_hsspi_probe()
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| D | pic32_spi.c | 66 ulong clk_rate; member
298 div = (priv->clk_rate / 2 / speed) - 1; in pic32_spi_set_speed()
402 priv->clk_rate = clk_get_periph_rate(clkdev, ret); in pic32_spi_probe()
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| /external/u-boot/drivers/net/ |
| D | zynq_gem.c | 362 unsigned long clk_rate = 0; in zynq_gem_init() local
454 clk_rate = ZYNQ_GEM_FREQUENCY_1000; in zynq_gem_init()
459 clk_rate = ZYNQ_GEM_FREQUENCY_100; in zynq_gem_init()
462 clk_rate = ZYNQ_GEM_FREQUENCY_10; in zynq_gem_init()
466 ret = clk_set_rate(&priv->clk, clk_rate); in zynq_gem_init()
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| /external/u-boot/drivers/mmc/ |
| D | msm_sdhci.c | 53 uint clk_rate = fdtdec_get_uint(gd->fdt_blob, node, "clock-frequency", in msm_sdc_clk_init() local
78 ret = clk_set_rate(&clk, clk_rate); in msm_sdc_clk_init()
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| D | gen_atmel_mci.c | 555 ulong clk_rate; local
568 clk_rate = clk_get_rate(&clk);
569 if (!clk_rate) {
574 priv->bus_clk_rate = clk_rate;
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| /external/u-boot/drivers/clk/ |
| D | clk-hsdk-cgu.c | 135 const u32 clk_rate[MAX_TUN_CLOCKS]; member
155 const u32 clk_rate[MAX_AXI_CLOCKS]; member
545 if (axi_clk_cfg.clk_rate[i] == rate) { in axi_clk_set()
583 if (tun_clk_cfg.clk_rate[i] == rate) { in tun_clk_set()
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| /external/u-boot/drivers/mtd/nand/ |
| D | sunxi_nand.c | 238 unsigned long clk_rate; member
277 unsigned long clk_rate; member
449 if (nfc->clk_rate != sunxi_nand->clk_rate) { in sunxi_nfc_select_chip()
450 sunxi_nfc_set_clk_rate(sunxi_nand->clk_rate); in sunxi_nfc_select_chip()
451 nfc->clk_rate = sunxi_nand->clk_rate; in sunxi_nfc_select_chip()
1341 chip->clk_rate = 1000000000L / min_clk_period; in sunxi_nand_chip_set_timings()
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