1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2011 Michal Simek
4 *
5 * Michal SIMEK <monstr@monstr.eu>
6 *
7 * Based on Xilinx gmac driver:
8 * (C) Copyright 2011 Xilinx
9 */
10
11 #include <clk.h>
12 #include <common.h>
13 #include <dm.h>
14 #include <net.h>
15 #include <netdev.h>
16 #include <config.h>
17 #include <console.h>
18 #include <malloc.h>
19 #include <asm/io.h>
20 #include <phy.h>
21 #include <miiphy.h>
22 #include <wait_bit.h>
23 #include <watchdog.h>
24 #include <asm/system.h>
25 #include <asm/arch/hardware.h>
26 #include <asm/arch/sys_proto.h>
27 #include <linux/errno.h>
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 /* Bit/mask specification */
32 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
33 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
34 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
35 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
36 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
37
38 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
39 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
40 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
41
42 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
43 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
44 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
45
46 /* Wrap bit, last descriptor */
47 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
48 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
49 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
50
51 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
52 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
53 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
54 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
55
56 #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */
57 #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
58 #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
59 #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
60 #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
61 #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
62 #ifdef CONFIG_ARM64
63 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */
64 #else
65 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */
66 #endif
67
68 #ifdef CONFIG_ARM64
69 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
70 #else
71 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
72 #endif
73
74 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
75 ZYNQ_GEM_NWCFG_FDEN | \
76 ZYNQ_GEM_NWCFG_FSREM | \
77 ZYNQ_GEM_NWCFG_MDCCLKDIV)
78
79 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
80
81 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
82 /* Use full configured addressable space (8 Kb) */
83 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
84 /* Use full configured addressable space (4 Kb) */
85 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
86 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
87 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
88
89 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
90 ZYNQ_GEM_DMACR_RXSIZE | \
91 ZYNQ_GEM_DMACR_TXSIZE | \
92 ZYNQ_GEM_DMACR_RXBUF)
93
94 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
95
96 #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000
97
98 /* Use MII register 1 (MII status register) to detect PHY */
99 #define PHY_DETECT_REG 1
100
101 /* Mask used to verify certain PHY features (or register contents)
102 * in the register above:
103 * 0x1000: 10Mbps full duplex support
104 * 0x0800: 10Mbps half duplex support
105 * 0x0008: Auto-negotiation support
106 */
107 #define PHY_DETECT_MASK 0x1808
108
109 /* TX BD status masks */
110 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
111 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
112 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
113
114 /* Clock frequencies for different speeds */
115 #define ZYNQ_GEM_FREQUENCY_10 2500000UL
116 #define ZYNQ_GEM_FREQUENCY_100 25000000UL
117 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
118
119 /* Device registers */
120 struct zynq_gem_regs {
121 u32 nwctrl; /* 0x0 - Network Control reg */
122 u32 nwcfg; /* 0x4 - Network Config reg */
123 u32 nwsr; /* 0x8 - Network Status reg */
124 u32 reserved1;
125 u32 dmacr; /* 0x10 - DMA Control reg */
126 u32 txsr; /* 0x14 - TX Status reg */
127 u32 rxqbase; /* 0x18 - RX Q Base address reg */
128 u32 txqbase; /* 0x1c - TX Q Base address reg */
129 u32 rxsr; /* 0x20 - RX Status reg */
130 u32 reserved2[2];
131 u32 idr; /* 0x2c - Interrupt Disable reg */
132 u32 reserved3;
133 u32 phymntnc; /* 0x34 - Phy Maintaince reg */
134 u32 reserved4[18];
135 u32 hashl; /* 0x80 - Hash Low address reg */
136 u32 hashh; /* 0x84 - Hash High address reg */
137 #define LADDR_LOW 0
138 #define LADDR_HIGH 1
139 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
140 u32 match[4]; /* 0xa8 - Type ID1 Match reg */
141 u32 reserved6[18];
142 #define STAT_SIZE 44
143 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
144 u32 reserved9[20];
145 u32 pcscntrl;
146 u32 reserved7[143];
147 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
148 u32 reserved8[15];
149 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
150 };
151
152 /* BD descriptors */
153 struct emac_bd {
154 u32 addr; /* Next descriptor pointer */
155 u32 status;
156 };
157
158 #define RX_BUF 32
159 /* Page table entries are set to 1MB, or multiples of 1MB
160 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
161 */
162 #define BD_SPACE 0x100000
163 /* BD separation space */
164 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
165
166 /* Setup the first free TX descriptor */
167 #define TX_FREE_DESC 2
168
169 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
170 struct zynq_gem_priv {
171 struct emac_bd *tx_bd;
172 struct emac_bd *rx_bd;
173 char *rxbuffers;
174 u32 rxbd_current;
175 u32 rx_first_buf;
176 int phyaddr;
177 int init;
178 struct zynq_gem_regs *iobase;
179 phy_interface_t interface;
180 struct phy_device *phydev;
181 int phy_of_handle;
182 struct mii_dev *bus;
183 struct clk clk;
184 u32 max_speed;
185 bool int_pcs;
186 };
187
phy_setup_op(struct zynq_gem_priv * priv,u32 phy_addr,u32 regnum,u32 op,u16 * data)188 static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
189 u32 op, u16 *data)
190 {
191 u32 mgtcr;
192 struct zynq_gem_regs *regs = priv->iobase;
193 int err;
194
195 err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
196 true, 20000, false);
197 if (err)
198 return err;
199
200 /* Construct mgtcr mask for the operation */
201 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
202 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
203 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
204
205 /* Write mgtcr and wait for completion */
206 writel(mgtcr, ®s->phymntnc);
207
208 err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
209 true, 20000, false);
210 if (err)
211 return err;
212
213 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
214 *data = readl(®s->phymntnc);
215
216 return 0;
217 }
218
phyread(struct zynq_gem_priv * priv,u32 phy_addr,u32 regnum,u16 * val)219 static int phyread(struct zynq_gem_priv *priv, u32 phy_addr,
220 u32 regnum, u16 *val)
221 {
222 int ret;
223
224 ret = phy_setup_op(priv, phy_addr, regnum,
225 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
226
227 if (!ret)
228 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
229 phy_addr, regnum, *val);
230
231 return ret;
232 }
233
phywrite(struct zynq_gem_priv * priv,u32 phy_addr,u32 regnum,u16 data)234 static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
235 u32 regnum, u16 data)
236 {
237 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
238 regnum, data);
239
240 return phy_setup_op(priv, phy_addr, regnum,
241 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
242 }
243
phy_detection(struct udevice * dev)244 static int phy_detection(struct udevice *dev)
245 {
246 int i;
247 u16 phyreg = 0;
248 struct zynq_gem_priv *priv = dev->priv;
249
250 if (priv->phyaddr != -1) {
251 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
252 if ((phyreg != 0xFFFF) &&
253 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
254 /* Found a valid PHY address */
255 debug("Default phy address %d is valid\n",
256 priv->phyaddr);
257 return 0;
258 } else {
259 debug("PHY address is not setup correctly %d\n",
260 priv->phyaddr);
261 priv->phyaddr = -1;
262 }
263 }
264
265 debug("detecting phy address\n");
266 if (priv->phyaddr == -1) {
267 /* detect the PHY address */
268 for (i = 31; i >= 0; i--) {
269 phyread(priv, i, PHY_DETECT_REG, &phyreg);
270 if ((phyreg != 0xFFFF) &&
271 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
272 /* Found a valid PHY address */
273 priv->phyaddr = i;
274 debug("Found valid phy address, %d\n", i);
275 return 0;
276 }
277 }
278 }
279 printf("PHY is not detected\n");
280 return -1;
281 }
282
zynq_gem_setup_mac(struct udevice * dev)283 static int zynq_gem_setup_mac(struct udevice *dev)
284 {
285 u32 i, macaddrlow, macaddrhigh;
286 struct eth_pdata *pdata = dev_get_platdata(dev);
287 struct zynq_gem_priv *priv = dev_get_priv(dev);
288 struct zynq_gem_regs *regs = priv->iobase;
289
290 /* Set the MAC bits [31:0] in BOT */
291 macaddrlow = pdata->enetaddr[0];
292 macaddrlow |= pdata->enetaddr[1] << 8;
293 macaddrlow |= pdata->enetaddr[2] << 16;
294 macaddrlow |= pdata->enetaddr[3] << 24;
295
296 /* Set MAC bits [47:32] in TOP */
297 macaddrhigh = pdata->enetaddr[4];
298 macaddrhigh |= pdata->enetaddr[5] << 8;
299
300 for (i = 0; i < 4; i++) {
301 writel(0, ®s->laddr[i][LADDR_LOW]);
302 writel(0, ®s->laddr[i][LADDR_HIGH]);
303 /* Do not use MATCHx register */
304 writel(0, ®s->match[i]);
305 }
306
307 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]);
308 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]);
309
310 return 0;
311 }
312
zynq_phy_init(struct udevice * dev)313 static int zynq_phy_init(struct udevice *dev)
314 {
315 int ret;
316 struct zynq_gem_priv *priv = dev_get_priv(dev);
317 struct zynq_gem_regs *regs = priv->iobase;
318 const u32 supported = SUPPORTED_10baseT_Half |
319 SUPPORTED_10baseT_Full |
320 SUPPORTED_100baseT_Half |
321 SUPPORTED_100baseT_Full |
322 SUPPORTED_1000baseT_Half |
323 SUPPORTED_1000baseT_Full;
324
325 /* Enable only MDIO bus */
326 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl);
327
328 if ((priv->interface != PHY_INTERFACE_MODE_SGMII) &&
329 (priv->interface != PHY_INTERFACE_MODE_GMII)) {
330 ret = phy_detection(dev);
331 if (ret) {
332 printf("GEM PHY init failed\n");
333 return ret;
334 }
335 }
336
337 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
338 priv->interface);
339 if (!priv->phydev)
340 return -ENODEV;
341
342 priv->phydev->supported &= supported | ADVERTISED_Pause |
343 ADVERTISED_Asym_Pause;
344 if (priv->max_speed) {
345 ret = phy_set_supported(priv->phydev, priv->max_speed);
346 if (ret)
347 return ret;
348 }
349
350 priv->phydev->advertising = priv->phydev->supported;
351
352 if (priv->phy_of_handle > 0)
353 dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle);
354
355 return phy_config(priv->phydev);
356 }
357
zynq_gem_init(struct udevice * dev)358 static int zynq_gem_init(struct udevice *dev)
359 {
360 u32 i, nwconfig;
361 int ret;
362 unsigned long clk_rate = 0;
363 struct zynq_gem_priv *priv = dev_get_priv(dev);
364 struct zynq_gem_regs *regs = priv->iobase;
365 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
366 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
367
368 if (!priv->init) {
369 /* Disable all interrupts */
370 writel(0xFFFFFFFF, ®s->idr);
371
372 /* Disable the receiver & transmitter */
373 writel(0, ®s->nwctrl);
374 writel(0, ®s->txsr);
375 writel(0, ®s->rxsr);
376 writel(0, ®s->phymntnc);
377
378 /* Clear the Hash registers for the mac address
379 * pointed by AddressPtr
380 */
381 writel(0x0, ®s->hashl);
382 /* Write bits [63:32] in TOP */
383 writel(0x0, ®s->hashh);
384
385 /* Clear all counters */
386 for (i = 0; i < STAT_SIZE; i++)
387 readl(®s->stat[i]);
388
389 /* Setup RxBD space */
390 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
391
392 for (i = 0; i < RX_BUF; i++) {
393 priv->rx_bd[i].status = 0xF0000000;
394 priv->rx_bd[i].addr =
395 ((ulong)(priv->rxbuffers) +
396 (i * PKTSIZE_ALIGN));
397 }
398 /* WRAP bit to last BD */
399 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
400 /* Write RxBDs to IP */
401 writel((ulong)priv->rx_bd, ®s->rxqbase);
402
403 /* Setup for DMA Configuration register */
404 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
405
406 /* Setup for Network Control register, MDIO, Rx and Tx enable */
407 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
408
409 /* Disable the second priority queue */
410 dummy_tx_bd->addr = 0;
411 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
412 ZYNQ_GEM_TXBUF_LAST_MASK|
413 ZYNQ_GEM_TXBUF_USED_MASK;
414
415 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
416 ZYNQ_GEM_RXBUF_NEW_MASK;
417 dummy_rx_bd->status = 0;
418
419 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr);
420 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr);
421
422 priv->init++;
423 }
424
425 ret = phy_startup(priv->phydev);
426 if (ret)
427 return ret;
428
429 if (!priv->phydev->link) {
430 printf("%s: No link.\n", priv->phydev->dev->name);
431 return -1;
432 }
433
434 nwconfig = ZYNQ_GEM_NWCFG_INIT;
435
436 /*
437 * Set SGMII enable PCS selection only if internal PCS/PMA
438 * core is used and interface is SGMII.
439 */
440 if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
441 priv->int_pcs) {
442 nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
443 ZYNQ_GEM_NWCFG_PCS_SEL;
444 #ifdef CONFIG_ARM64
445 writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
446 ®s->pcscntrl);
447 #endif
448 }
449
450 switch (priv->phydev->speed) {
451 case SPEED_1000:
452 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000,
453 ®s->nwcfg);
454 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
455 break;
456 case SPEED_100:
457 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100,
458 ®s->nwcfg);
459 clk_rate = ZYNQ_GEM_FREQUENCY_100;
460 break;
461 case SPEED_10:
462 clk_rate = ZYNQ_GEM_FREQUENCY_10;
463 break;
464 }
465
466 ret = clk_set_rate(&priv->clk, clk_rate);
467 if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
468 dev_err(dev, "failed to set tx clock rate\n");
469 return ret;
470 }
471
472 ret = clk_enable(&priv->clk);
473 if (ret && ret != -ENOSYS) {
474 dev_err(dev, "failed to enable tx clock\n");
475 return ret;
476 }
477
478 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
479 ZYNQ_GEM_NWCTRL_TXEN_MASK);
480
481 return 0;
482 }
483
zynq_gem_send(struct udevice * dev,void * ptr,int len)484 static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
485 {
486 u32 addr, size;
487 struct zynq_gem_priv *priv = dev_get_priv(dev);
488 struct zynq_gem_regs *regs = priv->iobase;
489 struct emac_bd *current_bd = &priv->tx_bd[1];
490
491 /* Setup Tx BD */
492 memset(priv->tx_bd, 0, sizeof(struct emac_bd));
493
494 priv->tx_bd->addr = (ulong)ptr;
495 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
496 ZYNQ_GEM_TXBUF_LAST_MASK;
497 /* Dummy descriptor to mark it as the last in descriptor chain */
498 current_bd->addr = 0x0;
499 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
500 ZYNQ_GEM_TXBUF_LAST_MASK|
501 ZYNQ_GEM_TXBUF_USED_MASK;
502
503 /* setup BD */
504 writel((ulong)priv->tx_bd, ®s->txqbase);
505
506 addr = (ulong) ptr;
507 addr &= ~(ARCH_DMA_MINALIGN - 1);
508 size = roundup(len, ARCH_DMA_MINALIGN);
509 flush_dcache_range(addr, addr + size);
510
511 addr = (ulong)priv->rxbuffers;
512 addr &= ~(ARCH_DMA_MINALIGN - 1);
513 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
514 flush_dcache_range(addr, addr + size);
515 barrier();
516
517 /* Start transmit */
518 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
519
520 /* Read TX BD status */
521 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
522 printf("TX buffers exhausted in mid frame\n");
523
524 return wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE,
525 true, 20000, true);
526 }
527
528 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
zynq_gem_recv(struct udevice * dev,int flags,uchar ** packetp)529 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
530 {
531 int frame_len;
532 u32 addr;
533 struct zynq_gem_priv *priv = dev_get_priv(dev);
534 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
535
536 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
537 return -1;
538
539 if (!(current_bd->status &
540 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
541 printf("GEM: SOF or EOF not set for last buffer received!\n");
542 return -1;
543 }
544
545 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
546 if (!frame_len) {
547 printf("%s: Zero size packet?\n", __func__);
548 return -1;
549 }
550
551 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
552 addr &= ~(ARCH_DMA_MINALIGN - 1);
553 *packetp = (uchar *)(uintptr_t)addr;
554
555 return frame_len;
556 }
557
zynq_gem_free_pkt(struct udevice * dev,uchar * packet,int length)558 static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
559 {
560 struct zynq_gem_priv *priv = dev_get_priv(dev);
561 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
562 struct emac_bd *first_bd;
563
564 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
565 priv->rx_first_buf = priv->rxbd_current;
566 } else {
567 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
568 current_bd->status = 0xF0000000; /* FIXME */
569 }
570
571 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
572 first_bd = &priv->rx_bd[priv->rx_first_buf];
573 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
574 first_bd->status = 0xF0000000;
575 }
576
577 if ((++priv->rxbd_current) >= RX_BUF)
578 priv->rxbd_current = 0;
579
580 return 0;
581 }
582
zynq_gem_halt(struct udevice * dev)583 static void zynq_gem_halt(struct udevice *dev)
584 {
585 struct zynq_gem_priv *priv = dev_get_priv(dev);
586 struct zynq_gem_regs *regs = priv->iobase;
587
588 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
589 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
590 }
591
zynq_board_read_rom_ethaddr(unsigned char * ethaddr)592 __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
593 {
594 return -ENOSYS;
595 }
596
zynq_gem_read_rom_mac(struct udevice * dev)597 static int zynq_gem_read_rom_mac(struct udevice *dev)
598 {
599 struct eth_pdata *pdata = dev_get_platdata(dev);
600
601 if (!pdata)
602 return -ENOSYS;
603
604 return zynq_board_read_rom_ethaddr(pdata->enetaddr);
605 }
606
zynq_gem_miiphy_read(struct mii_dev * bus,int addr,int devad,int reg)607 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
608 int devad, int reg)
609 {
610 struct zynq_gem_priv *priv = bus->priv;
611 int ret;
612 u16 val = 0;
613
614 ret = phyread(priv, addr, reg, &val);
615 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
616 return val;
617 }
618
zynq_gem_miiphy_write(struct mii_dev * bus,int addr,int devad,int reg,u16 value)619 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
620 int reg, u16 value)
621 {
622 struct zynq_gem_priv *priv = bus->priv;
623
624 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
625 return phywrite(priv, addr, reg, value);
626 }
627
zynq_gem_probe(struct udevice * dev)628 static int zynq_gem_probe(struct udevice *dev)
629 {
630 void *bd_space;
631 struct zynq_gem_priv *priv = dev_get_priv(dev);
632 int ret;
633
634 /* Align rxbuffers to ARCH_DMA_MINALIGN */
635 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
636 if (!priv->rxbuffers)
637 return -ENOMEM;
638
639 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
640
641 /* Align bd_space to MMU_SECTION_SHIFT */
642 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
643 if (!bd_space)
644 return -ENOMEM;
645
646 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
647 BD_SPACE, DCACHE_OFF);
648
649 /* Initialize the bd spaces for tx and rx bd's */
650 priv->tx_bd = (struct emac_bd *)bd_space;
651 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
652
653 ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
654 if (ret < 0) {
655 dev_err(dev, "failed to get clock\n");
656 return -EINVAL;
657 }
658
659 priv->bus = mdio_alloc();
660 priv->bus->read = zynq_gem_miiphy_read;
661 priv->bus->write = zynq_gem_miiphy_write;
662 priv->bus->priv = priv;
663
664 ret = mdio_register_seq(priv->bus, dev->seq);
665 if (ret)
666 return ret;
667
668 return zynq_phy_init(dev);
669 }
670
zynq_gem_remove(struct udevice * dev)671 static int zynq_gem_remove(struct udevice *dev)
672 {
673 struct zynq_gem_priv *priv = dev_get_priv(dev);
674
675 free(priv->phydev);
676 mdio_unregister(priv->bus);
677 mdio_free(priv->bus);
678
679 return 0;
680 }
681
682 static const struct eth_ops zynq_gem_ops = {
683 .start = zynq_gem_init,
684 .send = zynq_gem_send,
685 .recv = zynq_gem_recv,
686 .free_pkt = zynq_gem_free_pkt,
687 .stop = zynq_gem_halt,
688 .write_hwaddr = zynq_gem_setup_mac,
689 .read_rom_hwaddr = zynq_gem_read_rom_mac,
690 };
691
zynq_gem_ofdata_to_platdata(struct udevice * dev)692 static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
693 {
694 struct eth_pdata *pdata = dev_get_platdata(dev);
695 struct zynq_gem_priv *priv = dev_get_priv(dev);
696 int node = dev_of_offset(dev);
697 const char *phy_mode;
698
699 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
700 priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
701 /* Hardcode for now */
702 priv->phyaddr = -1;
703
704 priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node,
705 "phy-handle");
706 if (priv->phy_of_handle > 0)
707 priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
708 priv->phy_of_handle, "reg", -1);
709
710 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
711 if (phy_mode)
712 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
713 if (pdata->phy_interface == -1) {
714 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
715 return -EINVAL;
716 }
717 priv->interface = pdata->phy_interface;
718
719 priv->max_speed = fdtdec_get_uint(gd->fdt_blob, priv->phy_of_handle,
720 "max-speed", SPEED_1000);
721 priv->int_pcs = fdtdec_get_bool(gd->fdt_blob, node,
722 "is-internal-pcspma");
723
724 printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
725 priv->phyaddr, phy_string_for_interface(priv->interface));
726
727 return 0;
728 }
729
730 static const struct udevice_id zynq_gem_ids[] = {
731 { .compatible = "cdns,zynqmp-gem" },
732 { .compatible = "cdns,zynq-gem" },
733 { .compatible = "cdns,gem" },
734 { }
735 };
736
737 U_BOOT_DRIVER(zynq_gem) = {
738 .name = "zynq_gem",
739 .id = UCLASS_ETH,
740 .of_match = zynq_gem_ids,
741 .ofdata_to_platdata = zynq_gem_ofdata_to_platdata,
742 .probe = zynq_gem_probe,
743 .remove = zynq_gem_remove,
744 .ops = &zynq_gem_ops,
745 .priv_auto_alloc_size = sizeof(struct zynq_gem_priv),
746 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
747 };
748