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/external/u-boot/arch/arm/dts/
Dzynqmp-clk-ccf.dtsi14 clocks = <&clkc 71>;
20 clocks = <&clkc 72>;
26 clocks = <&clkc 73>;
32 clocks = <&clkc 74>;
74 clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
108 clocks = <&clkc 63>, <&clkc 31>;
112 clocks = <&clkc 64>, <&clkc 31>;
116 clocks = <&clkc 10>;
120 clocks = <&clkc 19>, <&clkc 31>;
124 clocks = <&clkc 19>, <&clkc 31>;
[all …]
Dzynqmp-clk.dtsi78 clocks = <&clk100 &clk100>;
82 clocks = <&clk100 &clk100>;
86 clocks = <&clk600>, <&clk100>;
90 clocks = <&clk600>, <&clk100>;
94 clocks = <&clk600>, <&clk100>;
98 clocks = <&clk600>, <&clk100>;
102 clocks = <&clk600>, <&clk100>;
106 clocks = <&clk600>, <&clk100>;
110 clocks = <&clk600>, <&clk100>;
114 clocks = <&clk600>, <&clk100>;
[all …]
Domap3xxx-clocks.dtsi20 …clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck…
27 clocks = <&osc_sys_ck>;
37 clocks = <&osc_sys_ck>;
45 clocks = <&dpll3_ck>;
53 clocks = <&dpll3_m2_ck>;
61 clocks = <&dpll4_ck>;
69 clocks = <&dpll3_m2x2_ck>;
77 clocks = <&sys_ck>;
87 clocks = <&core_96m_fck>, <&mcbsp_clks>;
95 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
[all …]
Dam33xx-clocks.dtsi14 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
22 clocks = <&sys_clkin_ck>;
30 clocks = <&sys_clkin_ck>;
38 clocks = <&sys_clkin_ck>;
46 clocks = <&sys_clkin_ck>;
54 clocks = <&sys_clkin_ck>;
62 clocks = <&sys_clkin_ck>;
70 clocks = <&sys_clkin_ck>;
78 clocks = <&sys_clkin_ck>;
86 clocks = <&sys_clkin_ck>;
[all …]
Ddra7xx-clocks.dtsi14 clocks = <&atl_gfclk_mux>;
20 clocks = <&atl_gfclk_mux>;
26 clocks = <&atl_gfclk_mux>;
32 clocks = <&atl_gfclk_mux>;
110 clocks = <&sys_clkin1>;
202 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
209 clocks = <&dpll_abe_ck>;
215 clocks = <&dpll_abe_x2_ck>;
226 clocks = <&dpll_abe_m2x2_ck>;
235 clocks = <&dpll_abe_ck>;
[all …]
Dam43xx-clocks.dtsi14 clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
22 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
30 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
38 clocks = <&sys_clkin_ck>;
46 clocks = <&sys_clkin_ck>;
54 clocks = <&sys_clkin_ck>;
62 clocks = <&sys_clkin_ck>;
70 clocks = <&sys_clkin_ck>;
78 clocks = <&sys_clkin_ck>;
86 clocks = <&sys_clkin_ck>;
[all …]
Dsocfpga.dtsi85 clocks = <&l4_main_clk>;
94 clocks = <&can0_clk>;
102 clocks = <&can1_clk>;
110 clocks {
139 clocks = <&osc1>;
145 clocks = <&main_pll>;
153 clocks = <&main_pll>;
161 clocks = <&main_pll>;
169 clocks = <&main_pll>;
176 clocks = <&main_pll>;
[all …]
Domap34xx-omap36xx-clocks.dtsi14 clocks = <&l4_ick>;
22 clocks = <&security_l4_ick2>;
30 clocks = <&security_l4_ick2>;
38 clocks = <&security_l4_ick2>;
46 clocks = <&security_l4_ick2>;
54 clocks = <&dpll4_m5x2_ck>;
63 clocks = <&l4_ick>;
71 clocks = <&core_96m_fck>;
79 clocks = <&l3_ick>;
87 clocks = <&security_l3_ick>;
[all …]
Domap36xx-am35xx-omap3430es2plus-clocks.dtsi14 clocks = <&corex2_fck>;
22 clocks = <&corex2_fck>;
31 clocks = <&sys_ck>, <&sys_ck>;
40 clocks = <&dpll5_ck>;
49 clocks = <&core_ck>;
57 clocks = <&core_ck>;
65 clocks = <&core_ck>;
73 clocks = <&core_ck>;
81 clocks = <&dpll4_m2x2_ck>;
89 clocks = <&core_ck>;
[all …]
Ddm816x-clocks.dtsi12 clocks = <&sys_clkin_ck &sys_clkin_ck>;
28 clocks = <&sys_clkin_ck &sys_clkin_ck>;
40 clocks = <&sys_clkin_ck &sys_clkin_ck>;
51 clocks = <&main_fapll 7>, < &sys_clkin_ck>;
92 clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1
100 clocks = <&clkout_pre_ck>;
109 clocks = <&clkout_div_ck>;
114 /* CM_DPLL clocks p1795 */
118 clocks = <&main_fapll 1>;
126 clocks = <&main_fapll 2>;
[all …]
Domap36xx-omap3430es2plus-clocks.dtsi14 clocks = <&corex2_fck>;
22 clocks = <&corex2_fck>;
31 clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
37 clocks = <&ssi_ssr_fck>;
45 clocks = <&core_l3_ick>;
53 clocks = <&l4_ick>;
61 clocks = <&ssi_l4_ick>;
69 clocks = <&omap_96m_fck>;
77 clocks = <&sys_ck>;
85 clocks = <&omap_96m_fck>;
[all …]
Dkeystone-clocks.dtsi11 clocks {
19 clocks = <&mainpllclk>, <&refclksys>;
29 clocks = <&mainmuxclk>;
38 clocks = <&mainmuxclk>;
47 clocks = <&mainmuxclk>;
57 clocks = <&mainmuxclk>;
67 clocks = <&chipclk1>;
76 clocks = <&chipclk1>;
85 clocks = <&papllclk>;
94 clocks = <&chipclk1>;
[all …]
Dkeystone-k2hk-clocks.dtsi11 clocks {
15 clocks = <&refclkarm>;
24 clocks = <&refclksys>;
32 clocks = <&refclkpass>;
41 clocks = <&refclkddr3a>;
50 clocks = <&refclkddr3b>;
59 clocks = <&chipclk16>;
69 clocks = <&chipclk1rstiso13>;
79 clocks = <&chipclk12>;
89 clocks = <&chipclk1>;
[all …]
Dsocfpga_arria10.dtsi80 clocks = <&l4_main_clk>;
97 clocks {
126 clocks = <&osc1>, <&cb_intosc_ls_clk>,
133 clocks = <&main_pll>;
140 clocks = <&main_pll>;
147 clocks = <&main_pll>;
154 clocks = <&main_pll>;
161 clocks = <&main_pll>;
168 clocks = <&main_pll>;
176 clocks = <&main_pll>;
[all …]
Dbcm283x.dtsi116 clocks: cprman@7e101000 { label
123 * pixel clocks come from the DSI analog PHY.
125 clocks = <&clk_osc>,
376 clocks = <&clocks BCM2835_CLOCK_UART>,
377 <&clocks BCM2835_CLOCK_VPU>;
386 clocks = <&clocks BCM2835_CLOCK_VPU>;
407 clocks = <&clocks BCM2835_CLOCK_VPU>;
417 clocks = <&clocks BCM2835_CLOCK_VPU>;
443 clocks = <&clocks BCM2835_PLLA_DSI0>,
444 <&clocks BCM2835_CLOCK_DSI0E>,
[all …]
Dkeystone-k2l-clocks.dtsi11 clocks {
15 clocks = <&refclksys>;
24 clocks = <&refclksys>;
32 clocks = <&refclksys>;
41 clocks = <&refclksys>;
50 clocks = <&chipclk12>;
60 clocks = <&chipclk12>;
70 clocks = <&chipclk1>;
80 clocks = <&chipclk1>;
90 clocks = <&chipclk1>;
[all …]
Dsama5d2.dtsi14 clocks {
37 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
45 clocks = <&utmi>, <&uhphs_clk>;
53 clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
61 clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
75 clocks = <&lcdc_clk>;
96 clocks = <&main>;
107 clocks = <&plla>;
113 clocks = <&main>;
119 clocks = <&audio_pll_frac>;
[all …]
Dstm32f429.dtsi50 clocks {
81 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
90 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
110 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
119 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
148 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
168 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
176 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
196 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
[all …]
Dsun4i-a10.dtsi68 clocks = <&ahb_gates 36>, <&ahb_gates 43>,
78 clocks = <&ahb_gates 36>, <&ahb_gates 43>,
89 clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>,
99 clocks = <&ahb_gates 34>, <&ahb_gates 36>,
115 clocks = <&cpu>;
166 clocks {
173 * other mux clocks when a specific parent clock is not
196 clocks = <&osc24M>;
211 clocks = <&osc24M>;
219 clocks = <&osc24M>;
[all …]
Dsun5i-gr8.dtsi62 clocks = <&cpu>;
66 clocks {
73 * other mux clocks when a specific parent clock is not
96 clocks = <&osc24M>;
111 clocks = <&osc24M>;
119 clocks = <&osc24M>;
128 clocks = <&osc3M>;
137 clocks = <&pll3>;
145 clocks = <&osc24M>;
153 clocks = <&osc24M>;
[all …]
Dsun5i.dtsi62 clocks = <&cpu>;
66 clocks {
73 * other mux clocks when a specific parent clock is not
96 clocks = <&osc24M>;
111 clocks = <&osc24M>;
119 clocks = <&osc24M>;
128 clocks = <&osc3M>;
137 clocks = <&pll3>;
145 clocks = <&osc24M>;
153 clocks = <&osc24M>;
[all …]
Dsun7i-a20.dtsi70 clocks = <&ahb_gates 36>, <&ahb_gates 43>,
80 clocks = <&ahb_gates 36>, <&ahb_gates 44>,
90 clocks = <&ahb_gates 34>, <&ahb_gates 36>,
106 clocks = <&cpu>;
180 clocks {
198 clocks = <&osc24M>;
213 clocks = <&osc24M>;
221 clocks = <&osc24M>;
230 clocks = <&osc3M>;
237 clocks = <&pll3>;
[all …]
Dimx7ulp.dtsi76 clocks {
159 clocks = <&clks IMX7ULP_CLK_DMA1>, <&clks IMX7ULP_CLK_DMA_MUX1>;
193 clocks = <&clks IMX7ULP_CLK_SNVS>;
201 clocks = <&clks IMX7ULP_CLK_LPTPM5>;
208 /* clocks = <&lpclk>;*/
209 clocks = <&clks IMX7ULP_CLK_LPIT1>;
211 assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>;
219 clocks = <&clks IMX7ULP_CLK_LPI2C4>;
221 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>;
231 clocks = <&clks IMX7ULP_CLK_LPI2C5>;
[all …]
Drk3xxx.dtsi45 clocks = <&cru ACLK_DMA1>;
56 clocks = <&cru ACLK_DMA1>;
68 clocks = <&cru ACLK_DMA2>;
96 clocks = <&cru CORE_PERI>;
103 clocks = <&cru CORE_PERI>;
121 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
132 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
146 clocks = <&cru HCLK_OTG0>;
162 clocks = <&cru HCLK_OTG1>;
179 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
[all …]
Dtegra30.dtsi39 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
95 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
108 clocks = <&tegra_car TEGRA30_CLK_MPE>;
117 clocks = <&tegra_car TEGRA30_CLK_VI>;
126 clocks = <&tegra_car TEGRA30_CLK_EPP>;
135 clocks = <&tegra_car TEGRA30_CLK_ISP>;
144 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
152 clocks = <&tegra_car TEGRA30_CLK_GR3D
164 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
183 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
[all …]

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