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Searched refs:cmplwi (Results 1 – 25 of 54) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dzext-and-cmp.ll10 define signext i32 @cmplwi(i32* nocapture readonly %p, i32* nocapture readonly %q, i32 signext %j, …
29 ; CHECK-LABEL: cmplwi:
32 ; CHECK-NOT: cmplwi
Drlwinm-zero-ext.ll10 ; CHECK-NOT: cmplwi [[REG]], 0
25 ; CHECK: cmplwi [[REG]], 0
43 ; CHECK-NOT: cmplwi [[REG]], 0
Dctrloops-softfloat.ll54 ; CHECK: cmplwi
77 ; CHECK: cmplwi
100 ; CHECK: cmplwi
123 ; CHECK: cmplwi
DPR35812-neg-cmpxchg.ll29 ; CHECK: cmplwi 3, 33059
32 ; CHECK: cmplwi 3, 234
65 ; CHECK-P7: cmplwi 3, 33059
67 ; CHECK-P7: cmplwi 3, 234
Dctrloops.ll26 ; CHECK-NOT: cmplwi
49 ; CHECK-NOT: cmplwi
73 ; CHECK-NOT: cmplwi
Dppc-shrink-wrapping.ll78 ; ENABLE: cmplwi 0, 3, 0
85 ; DISABLE: cmplwi 0, 3, 0
97 ; CHECK-NEXT: cmplwi [[IV]], 0
168 ; CHECK-NEXT: cmplwi [[IV]], 0
205 ; ENABLE: cmplwi 0, 3, 0
212 ; DISABLE: cmplwi 0, 3, 0
226 ; CHECK-NEXT: cmplwi [[IV]], 0
287 ; ENABLE: cmplwi 0, 3, 0
294 ; DISABLE: cmplwi 0, 3, 0
310 ; CHECK-NEXT: cmplwi [[IV]], 0
[all …]
Dbranch_coalesce.ll10 ; CHECK: cmplwi [[CMPR:[0-7]+]], 6, 0
27 ; CHECK-NOCOALESCE-NEXT: cmplwi 0, 6, 0
Dsdag-ppcf128.ll8 ; CHECK: cmplwi 3, 0
Dtail-dup-layout.ll190 ;CHECK-NEXT: cmplwi {{[0-9]+}}, 2
195 ;CHECK-O3-NEXT: cmplwi {{[0-9]+}}, 8
199 ;CHECK-O3-NEXT: cmplwi {{[0-9]+}}, 32
205 ;CHECK-O3-NEXT: cmplwi {{[0-9]+}}, 8
209 ;CHECK-O3-NEXT: cmplwi {{[0-9]+}}, 32
218 ;CHECK-O2-NEXT: cmplwi {{[0-9]+}}, 8
223 ;CHECK-O2-NEXT: cmplwi {{[0-9]+}}, 32
D2016-04-28-setjmp.ll11 ; CHECK: cmplwi 3, 0
Dppc-crbits-onoff.ll17 ; CHECK-DAG: cmplwi {{[0-9]+}}, 3, 0
DsimplifyConstCmpToISEL.ll7 ; CHECK-NEXT: cmplwi 0, 3, 1
/external/llvm/test/CodeGen/PowerPC/
Drlwinm-zero-ext.ll10 ; CHECK-NOT: cmplwi [[REG]], 0
25 ; CHECK: cmplwi [[REG]], 0
43 ; CHECK-NOT: cmplwi [[REG]], 0
Dctrloops-softfloat.ll54 ; CHECK: cmplwi
77 ; CHECK: cmplwi
100 ; CHECK: cmplwi
123 ; CHECK: cmplwi
Dctrloops.ll26 ; CHECK-NOT: cmplwi
49 ; CHECK-NOT: cmplwi
73 ; CHECK-NOT: cmplwi
Dppc-shrink-wrapping.ll78 ; ENABLE: cmplwi 0, 3, 0
85 ; DISABLE: cmplwi 0, 3, 0
97 ; CHECK-NEXT: cmplwi [[IV]], 0
168 ; CHECK-NEXT: cmplwi [[IV]], 0
205 ; ENABLE: cmplwi 0, 3, 0
212 ; DISABLE: cmplwi 0, 3, 0
224 ; CHECK-NEXT: cmplwi [[IV]], 0
285 ; ENABLE: cmplwi 0, 3, 0
292 ; DISABLE: cmplwi 0, 3, 0
306 ; CHECK-NEXT: cmplwi [[IV]], 0
[all …]
Dsdag-ppcf128.ll8 ; CHECK: cmplwi 3, 0
Dppc-crbits-onoff.ll15 ; CHECK-DAG: cmplwi {{[0-9]+}}, 3, 0
/external/u-boot/arch/powerpc/lib/
Dppcstring.S73 cmplwi 0,r5,4
115 2: cmplwi 0,r5,4
157 2: cmplwi 0,r5,4
/external/llvm/test/DebugInfo/PowerPC/
Dline.test5 ; branch, then further lowered to cmplwi + brcc but without the fidelity that
/external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/PowerPC/
Dline.test5 ; branch, then further lowered to cmplwi + brcc but without the fidelity that
/external/capstone/suite/MC/PowerPC/
Dppc64-encoding-ext.s.cs410 0x29,0x03,0x00,0x80 = cmplwi 2, 3, 128
411 0x28,0x03,0x00,0x80 = cmplwi 0, 3, 128
Dppc64-encoding.s.cs122 0x29,0x03,0x00,0x80 = cmplwi 2, 3, 128
/external/llvm/lib/Target/PowerPC/
DREADME.txt44 cmplwi cr0, r7, 143
398 cmplwi cr0, r3, 0
461 cmplwi cr0, r6, 33920
545 cmplwi cr0, r4, 32000
554 cmplwi cr0, r4, 32000
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DREADME.txt44 cmplwi cr0, r7, 143
398 cmplwi cr0, r3, 0
461 cmplwi cr0, r6, 33920
545 cmplwi cr0, r4, 32000
554 cmplwi cr0, r4, 32000

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