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Searched refs:cond_op (Results 1 – 14 of 14) sorted by relevance

/external/tensorflow/tensorflow/python/kernel_tests/
Dcond_v2_test.py161 cond_op = output.op.inputs[0].op
162 self.assertEqual(cond_op.type, "If")
163 return output, cond_op
177 cond_op = output.op.inputs[0].op
178 self.assertEqual(cond_op.type, "If")
179 return output, cond_op
183 _, cond_op = self._createCond(None)
184 self.assertEqual(cond_op.name, "cond")
186 cond_op.get_attr("then_branch").name, r"cond_true_\d*")
188 cond_op.get_attr("else_branch").name, r"cond_false_\d*")
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Dcontrol_flow_ops_py_test.py309 cond_op = control_flow_ops.loop_cond(less_op)
310 switch_i = control_flow_ops.switch(merge_i, cond_op)
335 cond_op = control_flow_ops.loop_cond(less_op)
336 switch_i = control_flow_ops.switch(merge_i, cond_op)
/external/mesa3d/src/compiler/nir/
Dnir_loop_analyze.c361 get_iteration(nir_op cond_op, nir_const_value *initial, nir_const_value *step, in get_iteration() argument
366 switch (cond_op) { in get_iteration()
401 nir_const_value *limit, nir_op cond_op, unsigned bit_size, in test_iterations() argument
405 assert(nir_op_infos[cond_op].num_inputs == 2); in test_iterations()
443 nir_const_value result = nir_eval_const_opcode(cond_op, 1, bit_size, src); in test_iterations()
/external/swiftshader/third_party/SPIRV-Tools/source/val/
Dvalidate_cfg.cpp127 const auto cond_op = _.FindDef(cond_id); in ValidateBranchConditional() local
128 if (!cond_op || !cond_op->type_id() || in ValidateBranchConditional()
129 !_.IsBoolScalarType(cond_op->type_id())) { in ValidateBranchConditional()
/external/deqp-deps/SPIRV-Tools/source/val/
Dvalidate_cfg.cpp127 const auto cond_op = _.FindDef(cond_id); in ValidateBranchConditional() local
128 if (!cond_op || !cond_op->type_id() || in ValidateBranchConditional()
129 !_.IsBoolScalarType(cond_op->type_id())) { in ValidateBranchConditional()
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsInstrInfo.td401 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>:
404 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> {
410 class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op,
414 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> {
422 class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op,
426 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))],
431 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
435 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))],
/external/llvm/lib/Target/Mips/
DMips64InstrInfo.td368 class SetCC64_R<string opstr, PatFrag cond_op> :
371 [(set GPR64Opnd:$rd, (zext (cond_op GPR64Opnd:$rs,
377 class SetCC64_I<string opstr, PatFrag cond_op>:
380 [(set GPR64Opnd:$rt, (zext (cond_op GPR64Opnd:$rs,
386 class CBranchBitNum<string opstr, DAGOperand opnd, PatFrag cond_op,
390 [(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)),
DMipsInstrInfo.td1248 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
1252 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], II_BCC,
1261 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
1265 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], II_BCCZ,
1275 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
1278 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
1281 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
1285 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
DMips16InstrInfo.td1389 class SetCC_R16<PatFrag cond_op, Instruction I>:
1390 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1393 class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
1394 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
DMicroMipsInstrInfo.td185 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMips64InstrInfo.td445 class SetCC64_R<string opstr, PatFrag cond_op> :
448 [(set GPR64Opnd:$rd, (zext (cond_op GPR64Opnd:$rs,
454 class SetCC64_I<string opstr, PatFrag cond_op>:
457 [(set GPR64Opnd:$rt, (zext (cond_op GPR64Opnd:$rs,
463 class CBranchBitNum<string opstr, DAGOperand opnd, PatFrag cond_op,
467 [(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)),
DMipsInstrInfo.td1516 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
1520 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], II_BCC,
1539 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
1543 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], II_BCCZ,
1563 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
1566 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
1569 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
1573 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
DMips16InstrInfo.td1395 class SetCC_R16<PatFrag cond_op, Instruction I>:
1396 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1399 class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
1400 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
DMicroMipsInstrInfo.td199 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,