Home
last modified time | relevance | path

Searched refs:constrainRegClass (Results 1 – 25 of 73) sorted by relevance

123

/external/llvm/lib/Target/AMDGPU/
DR600MachineScheduler.cpp375 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_XRegClass); in AssignSlot()
378 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_YRegClass); in AssignSlot()
381 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass); in AssignSlot()
384 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_WRegClass); in AssignSlot()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600MachineScheduler.cpp374 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_XRegClass); in AssignSlot()
377 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_YRegClass); in AssignSlot()
380 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_ZRegClass); in AssignSlot()
383 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_WRegClass); in AssignSlot()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp448 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass); in insertSelect()
454 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass); in insertSelect()
494 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) { in insertSelect()
498 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) { in insertSelect()
502 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) { in insertSelect()
505 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) { in insertSelect()
533 MRI.constrainRegClass(TrueReg, RC); in insertSelect()
534 MRI.constrainRegClass(FalseReg, RC); in insertSelect()
778 !MRI->constrainRegClass(Reg, OpRegCstraints)) in UpdateOperandRegClass()
2206 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass); in storeRegToStackSlot()
[all …]
DAArch64ConditionalCompares.cpp601 MRI->constrainRegClass(HeadCond[2].getReg(), in convert()
648 MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(), in convert()
651 MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(), in convert()
DAArch64RegisterInfo.cpp337 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DMachineRegisterInfo.cpp70 constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg, in constrainRegClass() function
86 MachineRegisterInfo::constrainRegClass(unsigned Reg, in constrainRegClass() function in MachineRegisterInfo
89 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); in constrainRegClass()
109 return ::constrainRegClass(*this, Reg, OldRC, RC, MinNumRegs); in constrainRegAttrs()
DTargetInstrInfo.cpp818 MRI.constrainRegClass(RegA, RC); in reassociateOps()
820 MRI.constrainRegClass(RegB, RC); in reassociateOps()
822 MRI.constrainRegClass(RegX, RC); in reassociateOps()
824 MRI.constrainRegClass(RegY, RC); in reassociateOps()
826 MRI.constrainRegClass(RegC, RC); in reassociateOps()
DOptimizePHIs.cpp180 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg))) in OptimizeBB()
DUnreachableBlockElim.cpp210 MRI.constrainRegClass(InputReg, MRI.getRegClass(OutputReg)) && in runOnMachineFunction()
DTailDuplicator.cpp242 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) { in tailDuplicateAndUpdate()
419 ConstrRC = MRI->constrainRegClass(VI->second.Reg, OrigRC); in duplicateInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp569 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass); in insertSelect()
575 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass); in insertSelect()
615 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) { in insertSelect()
619 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) { in insertSelect()
623 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) { in insertSelect()
626 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) { in insertSelect()
654 MRI.constrainRegClass(TrueReg, RC); in insertSelect()
655 MRI.constrainRegClass(FalseReg, RC); in insertSelect()
1205 !MRI->constrainRegClass(Reg, OpRegCstraints)) in UpdateOperandRegClass()
2762 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass); in storeRegToStackSlot()
[all …]
DAArch64ConditionalCompares.cpp644 MRI->constrainRegClass(HeadCond[2].getReg(), in convert()
691 MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(), in convert()
694 MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(), in convert()
/external/llvm/lib/CodeGen/
DTargetInstrInfo.cpp708 MRI.constrainRegClass(RegA, RC); in reassociateOps()
710 MRI.constrainRegClass(RegB, RC); in reassociateOps()
712 MRI.constrainRegClass(RegX, RC); in reassociateOps()
714 MRI.constrainRegClass(RegY, RC); in reassociateOps()
716 MRI.constrainRegClass(RegC, RC); in reassociateOps()
DOptimizePHIs.cpp171 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg))) in OptimizeBB()
DUnreachableBlockElim.cpp206 MRI.constrainRegClass(Input, MRI.getRegClass(Output)); in runOnMachineFunction()
DMachineCSE.cpp155 if (!MRI->constrainRegClass(SrcReg, RC)) in INITIALIZE_PASS_DEPENDENCY()
570 if (!MRI->constrainRegClass(NewReg, OldRC)) { in ProcessBlock()
DTailDuplicator.cpp209 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) { in tailDuplicateAndUpdate()
377 ConstrRC = MRI->constrainRegClass(VI->second.Reg, OrigRC); in duplicateInstruction()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DMachineCSE.cpp135 if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg))) in PerformTrivialCoalescing()
446 if (!MRI->constrainRegClass(NewReg, OldRC)) { in ProcessBlock()
DUnreachableBlockElim.cpp201 MRI.constrainRegClass(Input, MRI.getRegClass(Output)); in runOnMachineFunction()
DMachineRegisterInfo.cpp51 MachineRegisterInfo::constrainRegClass(unsigned Reg, in constrainRegClass() function in MachineRegisterInfo
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DMachineRegisterInfo.h226 const TargetRegisterClass *constrainRegClass(unsigned Reg,
/external/llvm/lib/Target/PowerPC/
DPPCVSXFMAMutate.cpp236 if (!MRI.constrainRegClass(KilledProdReg, in processBlock()
/external/llvm/lib/Target/ARM/
DThumb2InstrInfo.cpp153 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); in storeRegToStackSlot()
194 MRI->constrainRegClass(DestReg, in loadRegFromStackSlot()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DThumb2InstrInfo.cpp167 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); in storeRegToStackSlot()
210 MRI->constrainRegClass(DestReg, in loadRegFromStackSlot()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCVSXFMAMutate.cpp237 if (!MRI.constrainRegClass(KilledProdReg, in processBlock()

123