| /external/u-boot/arch/arm/mach-at91/arm926ejs/ |
| D | at91sam9261_devices.c | 58 void at91_spi0_hw_init(unsigned long cs_mask) in at91_spi0_hw_init() argument
66 if (cs_mask & (1 << 0)) { in at91_spi0_hw_init()
69 if (cs_mask & (1 << 1)) { in at91_spi0_hw_init()
72 if (cs_mask & (1 << 2)) { in at91_spi0_hw_init()
75 if (cs_mask & (1 << 3)) { in at91_spi0_hw_init()
78 if (cs_mask & (1 << 4)) { in at91_spi0_hw_init()
81 if (cs_mask & (1 << 5)) { in at91_spi0_hw_init()
84 if (cs_mask & (1 << 6)) { in at91_spi0_hw_init()
87 if (cs_mask & (1 << 7)) { in at91_spi0_hw_init()
92 void at91_spi1_hw_init(unsigned long cs_mask) in at91_spi1_hw_init() argument
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| D | at91sam9m10g45_devices.c | 59 void at91_spi0_hw_init(unsigned long cs_mask) in at91_spi0_hw_init() argument
67 if (cs_mask & (1 << 0)) { in at91_spi0_hw_init()
70 if (cs_mask & (1 << 1)) { in at91_spi0_hw_init()
73 if (cs_mask & (1 << 2)) { in at91_spi0_hw_init()
76 if (cs_mask & (1 << 3)) { in at91_spi0_hw_init()
79 if (cs_mask & (1 << 4)) { in at91_spi0_hw_init()
82 if (cs_mask & (1 << 5)) { in at91_spi0_hw_init()
85 if (cs_mask & (1 << 6)) { in at91_spi0_hw_init()
88 if (cs_mask & (1 << 7)) { in at91_spi0_hw_init()
93 void at91_spi1_hw_init(unsigned long cs_mask) in at91_spi1_hw_init() argument
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| D | at91sam9x5_devices.c | 110 void at91_spi0_hw_init(unsigned long cs_mask) in at91_spi0_hw_init() argument
118 if (cs_mask & (1 << 0)) in at91_spi0_hw_init()
120 if (cs_mask & (1 << 1)) in at91_spi0_hw_init()
122 if (cs_mask & (1 << 2)) in at91_spi0_hw_init()
124 if (cs_mask & (1 << 3)) in at91_spi0_hw_init()
126 if (cs_mask & (1 << 4)) in at91_spi0_hw_init()
128 if (cs_mask & (1 << 5)) in at91_spi0_hw_init()
130 if (cs_mask & (1 << 6)) in at91_spi0_hw_init()
132 if (cs_mask & (1 << 7)) in at91_spi0_hw_init()
136 void at91_spi1_hw_init(unsigned long cs_mask) in at91_spi1_hw_init() argument
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| D | at91sam9263_devices.c | 62 void at91_spi0_hw_init(unsigned long cs_mask) in at91_spi0_hw_init() argument
70 if (cs_mask & (1 << 0)) { in at91_spi0_hw_init()
73 if (cs_mask & (1 << 1)) { in at91_spi0_hw_init()
76 if (cs_mask & (1 << 2)) { in at91_spi0_hw_init()
79 if (cs_mask & (1 << 3)) { in at91_spi0_hw_init()
82 if (cs_mask & (1 << 4)) { in at91_spi0_hw_init()
85 if (cs_mask & (1 << 5)) { in at91_spi0_hw_init()
88 if (cs_mask & (1 << 6)) { in at91_spi0_hw_init()
91 if (cs_mask & (1 << 7)) { in at91_spi0_hw_init()
96 void at91_spi1_hw_init(unsigned long cs_mask) in at91_spi1_hw_init() argument
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| D | at91sam9260_devices.c | 61 void at91_spi0_hw_init(unsigned long cs_mask) in at91_spi0_hw_init() argument
69 if (cs_mask & (1 << 0)) { in at91_spi0_hw_init()
72 if (cs_mask & (1 << 1)) { in at91_spi0_hw_init()
75 if (cs_mask & (1 << 2)) { in at91_spi0_hw_init()
78 if (cs_mask & (1 << 3)) { in at91_spi0_hw_init()
81 if (cs_mask & (1 << 4)) { in at91_spi0_hw_init()
84 if (cs_mask & (1 << 5)) { in at91_spi0_hw_init()
87 if (cs_mask & (1 << 6)) { in at91_spi0_hw_init()
90 if (cs_mask & (1 << 7)) { in at91_spi0_hw_init()
95 void at91_spi1_hw_init(unsigned long cs_mask) in at91_spi1_hw_init() argument
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| D | at91sam9rl_devices.c | 58 void at91_spi0_hw_init(unsigned long cs_mask) in at91_spi0_hw_init() argument
66 if (cs_mask & (1 << 0)) { in at91_spi0_hw_init()
69 if (cs_mask & (1 << 1)) { in at91_spi0_hw_init()
72 if (cs_mask & (1 << 2)) { in at91_spi0_hw_init()
75 if (cs_mask & (1 << 3)) { in at91_spi0_hw_init()
78 if (cs_mask & (1 << 4)) { in at91_spi0_hw_init()
81 if (cs_mask & (1 << 5)) { in at91_spi0_hw_init()
84 if (cs_mask & (1 << 6)) { in at91_spi0_hw_init()
87 if (cs_mask & (1 << 7)) { in at91_spi0_hw_init()
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| D | at91sam9n12_devices.c | 54 void at91_spi0_hw_init(unsigned long cs_mask) in at91_spi0_hw_init() argument
62 if (cs_mask & (1 << 0)) in at91_spi0_hw_init()
64 if (cs_mask & (1 << 1)) in at91_spi0_hw_init()
66 if (cs_mask & (1 << 2)) in at91_spi0_hw_init()
68 if (cs_mask & (1 << 3)) in at91_spi0_hw_init()
72 void at91_spi1_hw_init(unsigned long cs_mask) in at91_spi1_hw_init() argument
80 if (cs_mask & (1 << 0)) in at91_spi1_hw_init()
82 if (cs_mask & (1 << 1)) in at91_spi1_hw_init()
84 if (cs_mask & (1 << 2)) in at91_spi1_hw_init()
86 if (cs_mask & (1 << 3)) in at91_spi1_hw_init()
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| /external/u-boot/arch/arm/mach-at91/armv7/ |
| D | sama5d3_devices.c | 89 void at91_spi0_hw_init(unsigned long cs_mask) in at91_spi0_hw_init() argument
95 if (cs_mask & (1 << 0)) in at91_spi0_hw_init()
97 if (cs_mask & (1 << 1)) in at91_spi0_hw_init()
99 if (cs_mask & (1 << 2)) in at91_spi0_hw_init()
101 if (cs_mask & (1 << 3)) in at91_spi0_hw_init()
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| /external/u-boot/arch/arm/mach-at91/include/mach/ |
| D | at91_common.h | 19 void at91_spi0_hw_init(unsigned long cs_mask);
20 void at91_spi1_hw_init(unsigned long cs_mask);
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| /external/u-boot/drivers/ddr/marvell/a38x/ |
| D | ddr3_training_leveling.c | 342 u32 c_cs, if_id, cs_mask = 0; in ddr3_tip_legacy_dynamic_write_leveling() local
356 cs_mask = cs_mask | 1 << (20 + c_cs); in ddr3_tip_legacy_dynamic_write_leveling()
362 TRAINING_REG, (0x80000008 | cs_mask), in ddr3_tip_legacy_dynamic_write_leveling()
383 u32 c_cs, if_id, cs_mask = 0; in ddr3_tip_legacy_dynamic_read_leveling() local
397 cs_mask = cs_mask | 1 << (20 + c_cs); in ddr3_tip_legacy_dynamic_read_leveling()
401 (0x80000040 | cs_mask), 0xffffffff)); in ddr3_tip_legacy_dynamic_read_leveling()
791 u32 *cs_mask) in ddr3_tip_calc_cs_mask() argument
798 *cs_mask = same_bus_cs = CS_BIT_MASK; in ddr3_tip_calc_cs_mask()
818 *cs_mask &= ~tm->interface_params[if_id]. in ddr3_tip_calc_cs_mask()
823 *cs_mask = (*cs_mask | (~(1 << effective_cs))) & CS_BIT_MASK; in ddr3_tip_calc_cs_mask()
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| D | ddr3_training_leveling.h | 13 u32 *cs_mask);
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| D | ddr3_training.c | 360 u32 cs_mask = 0; in hws_ddr3_tip_init_controller() local
476 cs_mask = 0; in hws_ddr3_tip_init_controller()
498 cs_mask |= in hws_ddr3_tip_init_controller()
504 if_id, cs_mask)); in hws_ddr3_tip_init_controller()
513 ((cs_mask & (1 << cs_cnt)) ? 1 in hws_ddr3_tip_init_controller()
1272 u32 cs_mask[MAX_INTERFACE_NUM]; in ddr3_tip_freq_set() local
1297 cs_mask[if_id] = CS_BIT_MASK; in ddr3_tip_freq_set()
1300 &cs_mask[if_id]); in ddr3_tip_freq_set()
1629 CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MR_CMD0, in ddr3_tip_freq_set()
1634 CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MR_CMD2, in ddr3_tip_freq_set()
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| D | ddr3_training_ip_prv_if.h | 36 u8 dev_num, u32 cs_mask, struct hws_cs_config_info *cs_info);
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