Searched refs:cwl (Results 1 – 8 of 8) sorted by relevance
25 unsigned int cwl; in mv_ddr_cwl_calc() local28 cwl = 9; in mv_ddr_cwl_calc()30 cwl = 10; in mv_ddr_cwl_calc()32 cwl = 11; in mv_ddr_cwl_calc()34 cwl = 12; in mv_ddr_cwl_calc()36 cwl = 0; in mv_ddr_cwl_calc()38 return cwl; in mv_ddr_cwl_calc()
576 u32 reg, tmp, cwl; local1089 cwl = 5; /* CWL = 5 */1091 cwl = 6; /* CWL = 6 */1093 cwl = 7; /* CWL = 7 */1095 cwl = 8; /* CWL = 8 */1097 cwl = 9; /* CWL = 9 */1099 cwl = 10; /* CWL = 10 */1101 cwl = 11; /* CWL = 11 */1103 cwl = 12; /* CWL = 12 */1105 cwl = 12; /* CWL = 12 */[all …]
998 reg |= (((dram_info->cwl) & REG_DFS_CWL_NEXT_STATE_MASK) << in ddr3_dfs_low_2_high()1184 reg |= ((dram_info->cwl) << REG_DDR3_MR2_CWL_OFFS); in ddr3_dfs_low_2_high()1496 reg |= dram_info->cwl << REG_DDR3_MR2_CWL_OFFS; in ddr3_dfs_low_2_high()
268 u32 cwl; member
145 dram_info.cwl = reg; in ddr3_hw_training()
122 u32 cwl; member253 spd->cwl = 0; in ddrtimingcalculation()255 spd->cwl = 1; in ddrtimingcalculation()257 spd->cwl = 2; in ddrtimingcalculation()259 spd->cwl = 3; in ddrtimingcalculation()261 spd->cwl = 4; in ddrtimingcalculation()263 spd->cwl = 5; in ddrtimingcalculation()356 (spd->cwl & 7) << 3 | (spd->pasr & 7); in init_ddr3param()370 (DYN_ODT & 3) << 22 | (spd->cwl & 0x7) << 14 | in init_ddr3param()
86 unsigned int cwl; in compute_cas_write_latency() local89 cwl = 9; in compute_cas_write_latency()91 cwl = 10; in compute_cas_write_latency()93 cwl = 11; in compute_cas_write_latency()95 cwl = 12; in compute_cas_write_latency()97 cwl = 14; in compute_cas_write_latency()99 cwl = 16; in compute_cas_write_latency()101 cwl = 18; in compute_cas_write_latency()103 return cwl; in compute_cas_write_latency()120 unsigned int cwl; in compute_cas_write_latency() local[all …]
262 uint8_t cwl; in ddrphy_init() local267 cwl = 5 + mrc_params->ddr_speed; in ddrphy_init()430 ((cwl - 2) << 0), 0x003f1f1f); in ddrphy_init()436 ((cwl - 2) << 0), 0x003f1f1f); in ddrphy_init()