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/external/bcc/tools/
Ddcsnoop_example.txt4 dcsnoop traces directory entry cache (dcache) lookups, and can be used for
6 dcache lookups are likely frequent. By default, only failed lookups are shown.
34 and the filename for the dcache lookup.
36 The way the dcache is currently implemented, each component of a path is
88 Trace directory entry cache (dcache) lookups
95 ./dcsnoop # trace failed dcache lookups
96 ./dcsnoop -a # trace all dcache lookups
Ddcstat_example.txt4 dcstat shows directory entry cache (dcache) statistics. For example:
21 took a slower code path to be processed ("SLOW/s"), the number of dcache misses
26 from the dcache, with a hit ration of 99.95%. A little later, starting at
/external/u-boot/doc/device-tree-bindings/cpu/
Dnios2.txt15 - dcache-line-size: Contains data cache line size.
17 - dcache-size: Contains data cache size.
38 dcache-line-size = <32>;
40 dcache-size = <32768>;
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.s.dcache.wb.ll3 declare void @llvm.amdgcn.s.dcache.wb() #0
11 call void @llvm.amdgcn.s.dcache.wb()
20 call void @llvm.amdgcn.s.dcache.wb()
Dllvm.amdgcn.s.dcache.wb.vol.ll3 declare void @llvm.amdgcn.s.dcache.wb.vol() #0
11 call void @llvm.amdgcn.s.dcache.wb.vol()
20 call void @llvm.amdgcn.s.dcache.wb.vol()
Dllvm.amdgcn.s.dcache.inv.ll4 declare void @llvm.amdgcn.s.dcache.inv() #0
13 call void @llvm.amdgcn.s.dcache.inv()
22 call void @llvm.amdgcn.s.dcache.inv()
Dllvm.amdgcn.s.dcache.inv.vol.ll4 declare void @llvm.amdgcn.s.dcache.inv.vol() #0
13 call void @llvm.amdgcn.s.dcache.inv.vol()
22 call void @llvm.amdgcn.s.dcache.inv.vol()
Dtarget-cpu.ll8 declare void @llvm.amdgcn.s.dcache.inv.vol() #0
11 declare void @llvm.amdgcn.s.dcache.wb() #0
58 call void @llvm.amdgcn.s.dcache.inv.vol()
75 call void @llvm.amdgcn.s.dcache.wb()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.s.dcache.wb.ll3 declare void @llvm.amdgcn.s.dcache.wb() #0
11 call void @llvm.amdgcn.s.dcache.wb()
20 call void @llvm.amdgcn.s.dcache.wb()
Dllvm.amdgcn.s.dcache.wb.vol.ll3 declare void @llvm.amdgcn.s.dcache.wb.vol() #0
11 call void @llvm.amdgcn.s.dcache.wb.vol()
20 call void @llvm.amdgcn.s.dcache.wb.vol()
Dllvm.amdgcn.s.dcache.inv.vol.ll4 declare void @llvm.amdgcn.s.dcache.inv.vol() #0
13 call void @llvm.amdgcn.s.dcache.inv.vol()
22 call void @llvm.amdgcn.s.dcache.inv.vol()
Dllvm.amdgcn.s.dcache.inv.ll4 declare void @llvm.amdgcn.s.dcache.inv() #0
13 call void @llvm.amdgcn.s.dcache.inv()
22 call void @llvm.amdgcn.s.dcache.inv()
Dtarget-cpu.ll8 declare void @llvm.amdgcn.s.dcache.inv.vol() #0
11 declare void @llvm.amdgcn.s.dcache.wb() #0
58 call void @llvm.amdgcn.s.dcache.inv.vol()
75 call void @llvm.amdgcn.s.dcache.wb()
/external/syzkaller/pkg/report/testdata/linux/report/
D877 [ 1722.511384] WARNING: CPU: 1 PID: 8922 at fs/dcache.c:1445 umount_check+0x246/0x2c0 fs/dcache.c:1…
/external/u-boot/board/synopsys/hsdk/
Dhsdk.c77 u32_env dcache; member
110 u32 dcache; member
126 { "dcache_ena", ENV_HEX, true, 0, 1, &env_common.dcache },
178 value = env_common.dcache.val; in sync_cross_cpu_data()
179 arc_write_uncached_32(&cross_cpu_data.dcache, value); in sync_cross_cpu_data()
208 if (arc_read_uncached_32(&cross_cpu_data.dcache)) in init_slave_cpu_func()
245 if (!env_common.dcache.val) in init_master_dcache()
249 if (env_common.dcache.val) in init_master_dcache()
/external/syzkaller/pkg/report/testdata/linux/guilty/
D51 FILE: fs/dcache.c
13 RIP: 0010:__d_lookup_rcu+0x27b/0xa10 fs/dcache.c:2144
46 RIP: __d_lookup_rcu+0x27b/0xa10 fs/dcache.c:2144 RSP: ffff880038466d18
/external/u-boot/common/
Dbootm_os.c345 int dcache; in do_bootm_qnxelf() local
364 dcache = dcache_status(); in do_bootm_qnxelf()
365 if (dcache) in do_bootm_qnxelf()
370 if (dcache) in do_bootm_qnxelf()
/external/u-boot/cmd/
Dcache.c101 dcache, 2, 1, do_dcache,
/external/u-boot/arch/nios2/dts/
D3c120_devboard.dts27 dcache-line-size = <32>;
29 dcache-size = <32768>;
D10m50_devboard.dts40 dcache-line-size = <32>;
41 dcache-size = <32768>;
/external/u-boot/arch/arm/mach-omap2/omap5/
Dsec_entry_cpu1.S85 add r1, r0, r1 @ dcache is not enabled on CPU1, so
/external/e2fsprogs/contrib/
Dfsstress.c235 int dcache[NDCACHE]; variable
713 dcache[dirid % NDCACHE] = slot; in dcache_enter()
721 dcache[i] = -1; in dcache_init()
729 i = dcache[dirid % NDCACHE]; in dcache_lookup()
739 dcp = &dcache[dirid % NDCACHE]; in dcache_purge()
/external/ltp/testcases/kernel/fs/fsstress/
Dfsstress.c208 int dcache[NDCACHE]; variable
686 dcache[dirid % NDCACHE] = slot; in dcache_enter()
694 dcache[i] = -1; in dcache_init()
702 i = dcache[dirid % NDCACHE]; in dcache_lookup()
712 dcp = &dcache[dirid % NDCACHE]; in dcache_purge()
/external/u-boot/arch/arm/cpu/armv8/
Dcache_v8.c658 #error Please describe your MMU layout in CONFIG_SYS_MEM_MAP and enable dcache.
/external/u-boot/board/freescale/m52277evb/
DREADME198 dcache - enable or disable data cache

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