| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/ |
| D | macro-ddivu.s | 6 ddivu $25,$11
9 # CHECK-NOTRAP: ddivu $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1f]
14 # CHECK-TRAP: ddivu $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1f]
17 ddivu $24,$12
20 # CHECK-NOTRAP: ddivu $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1f]
25 # CHECK-TRAP: ddivu $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1f]
28 ddivu $25,$0
32 ddivu $0,$9
35 # CHECK-NOTRAP: ddivu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1f]
40 # CHECK-TRAP: ddivu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1f]
[all …]
|
| D | macro-dremu.s | 9 # CHECK-NOTRAP: ddivu $zero, $4, $5 # encoding: [0x1f,0x00,0x85,0x00]
14 # CHECK-TRAP: ddivu $zero, $4, $5 # encoding: [0x1f,0x00,0x85,0x00]
35 # CHECK-NOTRAP: ddivu $zero, $4, $1 # encoding: [0x1f,0x00,0x81,0x00]
38 # CHECK-TRAP: ddivu $zero, $4, $1 # encoding: [0x1f,0x00,0x81,0x00]
43 # CHECK-NOTRAP: ddivu $zero, $4, $1 # encoding: [0x1f,0x00,0x81,0x00]
46 # CHECK-TRAP: ddivu $zero, $4, $1 # encoding: [0x1f,0x00,0x81,0x00]
52 # CHECK-NOTRAP: ddivu $zero, $4, $1 # encoding: [0x1f,0x00,0x81,0x00]
56 # CHECK-TRAP: ddivu $zero, $4, $1 # encoding: [0x1f,0x00,0x81,0x00]
61 # CHECK-NOTRAP: ddivu $zero, $4, $1 # encoding: [0x1f,0x00,0x81,0x00]
64 # CHECK-TRAP: ddivu $zero, $4, $1 # encoding: [0x1f,0x00,0x81,0x00]
[all …]
|
| D | macro-ddiv-bad.s | 11 ddivu $25, $11
14 ddivu $25, $0
17 ddivu $0,$0
|
| D | macro-ddivu-bad.s | 11 ddivu $25, $11
14 ddivu $25, $0
17 ddivu $0,$0
|
| /external/llvm/test/MC/Mips/ |
| D | macro-ddivu.s | 6 ddivu $25,$11
8 # CHECK-NOTRAP: ddivu $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1f]
12 ddivu $24,$12
14 # CHECK-NOTRAP: ddivu $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1f]
18 ddivu $25,$0
20 # CHECK-NOTRAP: ddivu $zero, $25, $zero # encoding: [0x03,0x20,0x00,0x1f]
24 ddivu $0,$9
26 # CHECK-NOTRAP: ddivu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1f]
30 ddivu $0,$0
32 # CHECK-NOTRAP: ddivu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1f]
[all …]
|
| D | macro-ddiv-bad.s | 11 ddivu $25, $11
14 ddivu $25, $0
17 ddivu $0,$0
|
| D | macro-ddivu-bad.s | 11 ddivu $25, $11
14 ddivu $25, $0
17 ddivu $0,$0
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
| D | mips64muldiv.ll | 44 ; ACC: ddivu $zero, $4, $5
46 ; GPR: ddivu $2, $4, $5
64 ; ACC: ddivu $zero, $4, $5
|
| D | mips64instrs.ll | 136 ; ACCMULDIV: ddivu $zero, $[[T0]], $[[T1]]
140 ; GPRMULDIV: ddivu $2, $[[T0]], $[[T1]]
168 ; ACCMULDIV: ddivu $zero, $4, $5
|
| D | divrem.ll | 285 ; GPR64: ddivu $2, $4, $5
366 ; ACC64: ddivu $zero, $4, $5
378 ; GPR64-DAG: ddivu $2, $4, $5
|
| /external/llvm/test/CodeGen/Mips/ |
| D | mips64muldiv.ll | 44 ; ACC: ddivu $zero, $4, $5
46 ; GPR: ddivu $2, $4, $5
64 ; ACC: ddivu $zero, $4, $5
|
| D | mips64instrs.ll | 140 ; ACCMULDIV: ddivu $zero, $[[T0]], $[[T1]]
144 ; GPRMULDIV: ddivu $2, $[[T0]], $[[T1]]
172 ; ACCMULDIV: ddivu $zero, $4, $5
|
| D | divrem.ll | 285 ; GPR64: ddivu $2, $4, $5
366 ; ACC64: ddivu $zero, $4, $5
373 ; GPR64-DAG: ddivu $2, $4, $5
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | udiv.ll | 130 ; GP64-NOT-R6: ddivu $zero, $4, $5
134 ; 64R6: ddivu $2, $4, $5
139 ; MM64: ddivu $2, $4, $5
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
| D | mips64instrs.ll | 97 ; CHECK: ddivu $zero
113 ; CHECK: ddivu $zero
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | udiv.ll | 128 ; GP64-NOT-R6: ddivu $zero, $4, $5
132 ; 64R6: ddivu $2, $4, $5
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r6/ |
| D | invalid-mips3.s | 31 # ddivu has been re-encoded. See valid.s
|
| D | invalid-mips64.s | 52 # ddivu has been re-encoded. See valid.s
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| D | invalid-mips3.s | 31 # ddivu has been re-encoded. See valid.s
|
| D | invalid-mips64.s | 52 # ddivu has been re-encoded. See valid.s
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 310 def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,
1063 "ddivu\t$rd, $rs, $rt">,
1067 "ddivu\t$rd, $rs, $imm">,
1083 // GAS expands 'divu' and 'ddivu' differently when the destination
1085 // form. 'ddivu' gets expanded, while 'divu' is not expanded.
1087 def : MipsInstAlias<"ddivu $rt, $rs", (DUDivMacro GPR64Opnd:$rt,
1091 def : MipsInstAlias<"ddivu $rd, $imm", (DUDivIMacro GPR64Opnd:$rd,
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| D | invalid.s | 79 ddivu $32, $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
80 ddivu $3, $34, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
81 ddivu $3, $4, $35 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/MC/Mips/mips2/ |
| D | invalid-mips3.s | 21 …ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips2/ |
| D | invalid-mips3.s | 21 …ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
|
| /external/llvm/lib/Target/Mips/ |
| D | MicroMips64r6InstrInfo.td | 29 class DDIVU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddivu", 0b110011000>;
129 class DDIVU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddivu", GPR64Opnd, udiv>;
|