1; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ 2; RUN: -check-prefixes=ALL,NOT-R6,GP32 3; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ 4; RUN: -check-prefixes=ALL,NOT-R6,GP32 5; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ 6; RUN: -check-prefixes=ALL,NOT-R6,GP32 7; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ 8; RUN: -check-prefixes=ALL,NOT-R6,GP32 9; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ 10; RUN: -check-prefixes=ALL,NOT-R6,GP32 11; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ 12; RUN: -check-prefixes=ALL,R6,GP32 13 14; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ 15; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 16; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ 17; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 18; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ 19; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 20; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ 21; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 22; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ 23; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 24; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ 25; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 26; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ 27; RUN: -check-prefixes=ALL,R6,64R6 28 29; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ 30; RUN: -check-prefixes=ALL,MMR3,MM32 31; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ 32; RUN: -check-prefixes=ALL,MMR6,MM32 33 34define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) { 35entry: 36; ALL-LABEL: udiv_i1: 37 38 ; NOT-R6: divu $zero, $4, $5 39 ; NOT-R6: teq $5, $zero, 7 40 ; NOT-R6: mflo $2 41 42 ; R6: divu $2, $4, $5 43 ; R6: teq $5, $zero, 7 44 45 ; MMR3: divu $zero, $4, $5 46 ; MMR3: teq $5, $zero, 7 47 ; MMR3: mflo16 $2 48 49 ; MMR6: divu $2, $4, $5 50 ; MMR6: teq $5, $zero, 7 51 52 %r = udiv i1 %a, %b 53 ret i1 %r 54} 55 56define zeroext i8 @udiv_i8(i8 zeroext %a, i8 zeroext %b) { 57entry: 58; ALL-LABEL: udiv_i8: 59 60 ; NOT-R6: divu $zero, $4, $5 61 ; NOT-R6: teq $5, $zero, 7 62 ; NOT-R6: mflo $2 63 64 ; R6: divu $2, $4, $5 65 ; R6: teq $5, $zero, 7 66 67 ; MMR3: divu $zero, $4, $5 68 ; MMR3: teq $5, $zero, 7 69 ; MMR3: mflo16 $2 70 71 ; MMR6: divu $2, $4, $5 72 ; MMR6: teq $5, $zero, 7 73 74 %r = udiv i8 %a, %b 75 ret i8 %r 76} 77 78define zeroext i16 @udiv_i16(i16 zeroext %a, i16 zeroext %b) { 79entry: 80; ALL-LABEL: udiv_i16: 81 82 ; NOT-R6: divu $zero, $4, $5 83 ; NOT-R6: teq $5, $zero, 7 84 ; NOT-R6: mflo $2 85 86 ; R6: divu $2, $4, $5 87 ; R6: teq $5, $zero, 7 88 89 ; MMR3: divu $zero, $4, $5 90 ; MMR3: teq $5, $zero, 7 91 ; MMR3: mflo16 $2 92 93 ; MMR6: divu $2, $4, $5 94 ; MMR6: teq $5, $zero, 7 95 96 %r = udiv i16 %a, %b 97 ret i16 %r 98} 99 100define signext i32 @udiv_i32(i32 signext %a, i32 signext %b) { 101entry: 102; ALL-LABEL: udiv_i32: 103 104 ; NOT-R6: divu $zero, $4, $5 105 ; NOT-R6: teq $5, $zero, 7 106 ; NOT-R6: mflo $2 107 108 ; R6: divu $2, $4, $5 109 ; R6: teq $5, $zero, 7 110 111 ; MMR3: divu $zero, $4, $5 112 ; MMR3: teq $5, $zero, 7 113 ; MMR3: mflo16 $2 114 115 ; MMR6: divu $2, $4, $5 116 ; MMR6: teq $5, $zero, 7 117 118 %r = udiv i32 %a, %b 119 ret i32 %r 120} 121 122define signext i64 @udiv_i64(i64 signext %a, i64 signext %b) { 123entry: 124; ALL-LABEL: udiv_i64: 125 126 ; GP32: lw $25, %call16(__udivdi3)($gp) 127 128 ; GP64-NOT-R6: ddivu $zero, $4, $5 129 ; GP64-NOT-R6: teq $5, $zero, 7 130 ; GP64-NOT-R6: mflo $2 131 132 ; 64R6: ddivu $2, $4, $5 133 ; 64R6: teq $5, $zero, 7 134 135 ; MM32: lw $25, %call16(__udivdi3)($2) 136 137 %r = udiv i64 %a, %b 138 ret i64 %r 139} 140 141define signext i128 @udiv_i128(i128 signext %a, i128 signext %b) { 142entry: 143; ALL-LABEL: udiv_i128: 144 145 ; GP32: lw $25, %call16(__udivti3)($gp) 146 147 ; GP64-NOT-R6: ld $25, %call16(__udivti3)($gp) 148 ; 64-R6: ld $25, %call16(__udivti3)($gp) 149 150 ; MM32: lw $25, %call16(__udivti3)($16) 151 152 %r = udiv i128 %a, %b 153 ret i128 %r 154} 155