| /external/iproute2/devlink/ |
| D | devlink.c | 203 struct dl { struct
222 static int dl_argc(struct dl *dl) in dl_argc() argument
224 return dl->argc; in dl_argc()
227 static char *dl_argv(struct dl *dl) in dl_argv() argument
229 if (dl_argc(dl) == 0) in dl_argv()
231 return *dl->argv; in dl_argv()
234 static void dl_arg_inc(struct dl *dl) in dl_arg_inc() argument
236 if (dl_argc(dl) == 0) in dl_arg_inc()
238 dl->argc--; in dl_arg_inc()
239 dl->argv++; in dl_arg_inc()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 201 const SDLoc &dl, SelectionDAG &DAG) const { in getInt() argument
203 IntOps.push_back(DAG.getConstant(IntId, dl, MVT::i32)); in getInt()
206 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, ResTy, IntOps); in getInt()
251 HexagonTargetLowering::opJoin(const VectorPair &Ops, const SDLoc &dl, in opJoin() argument
253 return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)), in opJoin()
258 HexagonTargetLowering::opSplit(SDValue Vec, const SDLoc &dl, in opSplit() argument
263 return DAG.SplitVector(Vec, dl, Tys.first, Tys.second); in opSplit()
289 const SDLoc &dl(ElemIdx); in convertToByteIndex() local
290 return DAG.getNode(ISD::SHL, dl, MVT::i32, in convertToByteIndex()
291 {ElemIdx, DAG.getConstant(L, dl, MVT::i32)}); in convertToByteIndex()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 124 const SDLoc &dl);
126 const SDLoc &dl);
132 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, const SDLoc &dl,
137 bool &NeedInvert, const SDLoc &dl);
141 unsigned NumOps, bool isSigned, const SDLoc &dl);
159 const SDLoc &dl);
171 const SDLoc &dl);
173 const SDLoc &dl);
175 const SDLoc &dl);
177 SDValue ExpandBITREVERSE(SDValue Op, const SDLoc &dl);
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| D | LegalizeIntegerTypes.cpp | 257 SDLoc dl(N); in PromoteIntRes_BITCAST() local
265 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); in PromoteIntRes_BITCAST()
269 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
273 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp)); in PromoteIntRes_BITCAST()
282 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
296 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
300 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); in PromoteIntRes_BITCAST()
307 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); in PromoteIntRes_BITCAST()
310 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
318 SDLoc dl(N); in PromoteIntRes_BSWAP() local
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| D | LegalizeTypesGeneric.cpp | 46 SDLoc dl(N); in ExpandRes_BITCAST() local
63 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
64 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
75 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
76 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
83 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
84 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
89 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
90 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
97 std::tie(Lo, Hi) = DAG.SplitVector(InOp, dl, LoVT, HiVT); in ExpandRes_BITCAST()
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| D | TargetLowering.cpp | 121 const SDLoc &dl, bool doesNotReturn, in makeLibCall() argument
143 CLI.setDebugLoc(dl) in makeLibCall()
158 const SDLoc &dl) const { in softenSetCCOperands()
261 dl).first; in softenSetCCOperands()
262 NewRHS = DAG.getConstant(0, dl, RetVT); in softenSetCCOperands()
270 ISD::SETCC, dl, in softenSetCCOperands()
274 dl).first; in softenSetCCOperands()
276 ISD::SETCC, dl, in softenSetCCOperands()
279 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS); in softenSetCCOperands()
397 SDLoc dl(Op); in ShrinkDemandedOp() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 97 const SDLoc &dl);
99 const SDLoc &dl);
105 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, const SDLoc &dl,
110 bool &NeedInvert, const SDLoc &dl);
114 unsigned NumOps, bool isSigned, const SDLoc &dl);
132 const SDLoc &dl);
144 const SDLoc &dl);
146 const SDLoc &dl);
148 const SDLoc &dl);
150 SDValue ExpandBITREVERSE(SDValue Op, const SDLoc &dl);
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| D | LegalizeIntegerTypes.cpp | 255 SDLoc dl(N); in PromoteIntRes_BITCAST() local
263 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); in PromoteIntRes_BITCAST()
267 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
271 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp); in PromoteIntRes_BITCAST()
280 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
294 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
298 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); in PromoteIntRes_BITCAST()
305 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); in PromoteIntRes_BITCAST()
308 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
316 SDLoc dl(N); in PromoteIntRes_BSWAP() local
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| D | LegalizeTypesGeneric.cpp | 46 SDLoc dl(N); in ExpandRes_BITCAST() local
63 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
64 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
75 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
76 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
83 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
84 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
89 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
90 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
97 std::tie(Lo, Hi) = DAG.SplitVector(InOp, dl, LoVT, HiVT); in ExpandRes_BITCAST()
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| D | TargetLowering.cpp | 119 const SDLoc &dl, bool doesNotReturn, in makeLibCall() argument
141 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode()) in makeLibCall()
153 const SDLoc &dl) const { in softenSetCCOperands()
256 dl).first; in softenSetCCOperands()
257 NewRHS = DAG.getConstant(0, dl, RetVT); in softenSetCCOperands()
265 ISD::SETCC, dl, in softenSetCCOperands()
269 dl).first; in softenSetCCOperands()
271 ISD::SETCC, dl, in softenSetCCOperands()
274 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS); in softenSetCCOperands()
342 SDLoc dl(Op); in ShrinkDemandedConstant() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 166 inline SDValue getI16Imm(unsigned Imm, const SDLoc &dl) { in getI16Imm() argument
167 return CurDAG->getTargetConstant(Imm, dl, MVT::i16); in getI16Imm()
172 inline SDValue getI32Imm(unsigned Imm, const SDLoc &dl) { in getI32Imm() argument
173 return CurDAG->getTargetConstant(Imm, dl, MVT::i32); in getI32Imm()
178 inline SDValue getI64Imm(uint64_t Imm, const SDLoc &dl) { in getI64Imm() argument
179 return CurDAG->getTargetConstant(Imm, dl, MVT::i64); in getI64Imm()
183 inline SDValue getSmallIPtrImm(unsigned Imm, const SDLoc &dl) { in getSmallIPtrImm() argument
185 Imm, dl, PPCLowering->getPointerTy(CurDAG->getDataLayout())); in getSmallIPtrImm()
218 const SDLoc &dl);
293 SDLoc dl(Op); in SelectInlineAsmMemoryOperand() local
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 98 SDValue Idx, DebugLoc dl);
100 SDValue Idx, DebugLoc dl);
106 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
114 DebugLoc dl);
118 unsigned NumOps, bool isSigned, DebugLoc dl);
133 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
140 DebugLoc dl);
142 DebugLoc dl);
144 DebugLoc dl);
146 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
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| D | LegalizeTypesGeneric.cpp | 45 DebugLoc dl = N->getDebugLoc(); in ExpandRes_BITCAST() local
57 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
58 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
64 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
65 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
71 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
72 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
77 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
78 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
85 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, in ExpandRes_BITCAST()
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| D | LegalizeIntegerTypes.cpp | 211 DebugLoc dl = N->getDebugLoc(); in PromoteIntRes_BITCAST() local
222 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); in PromoteIntRes_BITCAST()
226 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
233 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
247 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
251 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); in PromoteIntRes_BITCAST()
256 return DAG.getNode(ISD::BITCAST, dl, OutVT, GetWidenedVector(InOp)); in PromoteIntRes_BITCAST()
259 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
267 DebugLoc dl = N->getDebugLoc(); in PromoteIntRes_BSWAP() local
270 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), in PromoteIntRes_BSWAP()
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 288 DebugLoc dl = ADDENode->getDebugLoc(); in SelectMadd() local
293 SDValue MAdd = CurDAG->getNode(MultOpc, dl, in SelectMadd()
301 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, in SelectMadd()
303 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, in SelectMadd()
362 DebugLoc dl = SUBENode->getDebugLoc(); in SelectMsub() local
367 SDValue MSub = CurDAG->getNode(MultOpc, dl, in SelectMsub()
375 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, in SelectMsub()
377 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, in SelectMsub()
426 DebugLoc dl = N->getDebugLoc(); in PerformDivRemCombine() local
428 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, in PerformDivRemCombine()
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| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaISelLowering.cpp | 199 DebugLoc dl = Op.getDebugLoc(); in LowerJumpTable() local
201 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, JTI, in LowerJumpTable()
203 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, JTI, Hi); in LowerJumpTable()
235 DebugLoc dl, SelectionDAG &DAG, in LowerCall() argument
268 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
271 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
274 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
286 StackPtr = DAG.getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64); in LowerCall()
288 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), in LowerCall()
292 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, in LowerCall()
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| /external/llvm/lib/Target/X86/ |
| D | X86SelectionDAGInfo.cpp | 48 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, in EmitTargetCodeForMemset() argument
88 CLI.setDebugLoc(dl).setChain(Chain) in EmitTargetCodeForMemset()
133 Count = DAG.getIntPtrConstant(SizeVal, dl); in EmitTargetCodeForMemset()
139 Count = DAG.getIntPtrConstant(SizeVal / UBytes, dl); in EmitTargetCodeForMemset()
143 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT), in EmitTargetCodeForMemset()
148 Count = DAG.getIntPtrConstant(SizeVal, dl); in EmitTargetCodeForMemset()
149 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag); in EmitTargetCodeForMemset()
153 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX, in EmitTargetCodeForMemset()
156 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RDI : X86::EDI, in EmitTargetCodeForMemset()
162 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops); in EmitTargetCodeForMemset()
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| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 558 DebugLoc dl = Op.getDebugLoc(); in LowerLOAD() local
598 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, in LowerLOAD()
618 rotate = DAG.getNode(ISD::ADD, dl, PtrVT, in LowerLOAD()
637 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1); in LowerLOAD()
638 the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag); in LowerLOAD()
639 basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT); in LowerLOAD()
643 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1); in LowerLOAD()
646 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, in LowerLOAD()
653 rotate = DAG.getNode(ISD::ADD, dl, PtrVT, in LowerLOAD()
659 SDValue low = DAG.getLoad(MVT::i128, dl, the_chain, basePtr, in LowerLOAD()
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| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 85 DebugLoc dl, SelectionDAG &DAG) const { in LowerReturn() argument
114 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
128 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); in LowerReturn()
129 Chain = DAG.getCopyToReg(Chain, dl, SP::I0, Val, Flag); in LowerReturn()
139 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, in LowerReturn()
141 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, in LowerReturn()
153 DebugLoc dl, SelectionDAG &DAG, in LowerFormalArguments() argument
176 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, in LowerFormalArguments()
188 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); in LowerFormalArguments()
198 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, in LowerFormalArguments()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 94 inline SDValue getI32Imm(unsigned Imm, const SDLoc &dl) { in getI32Imm() argument
95 return CurDAG->getTargetConstant(Imm, dl, MVT::i32); in getI32Imm()
100 inline SDValue getI64Imm(uint64_t Imm, const SDLoc &dl) { in getI64Imm() argument
101 return CurDAG->getTargetConstant(Imm, dl, MVT::i64); in getI64Imm()
105 inline SDValue getSmallIPtrImm(unsigned Imm, const SDLoc &dl) { in getSmallIPtrImm() argument
107 Imm, dl, PPCLowering->getPointerTy(CurDAG->getDataLayout())); in getSmallIPtrImm()
131 const SDLoc &dl);
203 SDLoc dl(Op); in SelectInlineAsmMemoryOperand() local
204 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32); in SelectInlineAsmMemoryOperand()
207 dl, Op.getValueType(), in SelectInlineAsmMemoryOperand()
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| D | PPCISelLowering.cpp | 1851 SDLoc dl(N); in SelectAddressRegImm() local
1860 Disp = DAG.getTargetConstant(imm, dl, N.getValueType()); in SelectAddressRegImm()
1900 Disp = DAG.getTargetConstant(imm, dl, N.getValueType()); in SelectAddressRegImm()
1911 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0)); in SelectAddressRegImm()
1924 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32); in SelectAddressRegImm()
1926 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl, in SelectAddressRegImm()
1929 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0); in SelectAddressRegImm()
1934 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout())); in SelectAddressRegImm()
2114 static SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, bool Is64Bit, in getTOCEntry() argument
2118 DAG.getNode(PPCISD::GlobalBaseReg, dl, VT); in getTOCEntry()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 255 SDLoc dl(GA); in getGlobalAddressWrapper() local
258 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
263 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
265 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
330 SDLoc dl(CP); in LowerConstantPool() local
340 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res); in LowerConstantPool()
353 SDLoc dl(Op); in LowerBR_JT() local
362 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index); in LowerBR_JT()
365 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, in LowerBR_JT()
366 DAG.getConstant(1, dl, MVT::i32)); in LowerBR_JT()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 252 SDLoc dl(GA); in getGlobalAddressWrapper() local
255 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
260 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
262 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
326 SDLoc dl(CP); in LowerConstantPool() local
336 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res); in LowerConstantPool()
349 SDLoc dl(Op); in LowerBR_JT() local
358 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index); in LowerBR_JT()
361 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, in LowerBR_JT()
362 DAG.getConstant(1, dl, MVT::i32)); in LowerBR_JT()
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| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 216 DebugLoc dl = Op.getDebugLoc(); in LowerSELECT_CC() local
217 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2), in LowerSELECT_CC()
219 return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0), in LowerSELECT_CC()
228 DebugLoc dl = GA.getDebugLoc(); in getGlobalAddressWrapper() local
230 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
240 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
242 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
253 static inline SDValue BuildGetId(SelectionDAG &DAG, DebugLoc dl) { in BuildGetId() argument
254 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, in BuildGetId()
267 DebugLoc dl = Op.getDebugLoc(); in LowerGlobalTLSAddress() local
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 854 DebugLoc dl = N.getDebugLoc(); in SelectAddressRegImm() local
923 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0); in SelectAddressRegImm()
970 DebugLoc dl = N.getDebugLoc(); in SelectAddressRegImmShift() local
1037 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0); in SelectAddressRegImmShift()
1232 DebugLoc dl = Op.getDebugLoc(); in LowerSETCC() local
1243 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); in LowerSETCC()
1246 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); in LowerSETCC()
1247 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, in LowerSETCC()
1249 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); in LowerSETCC()
1266 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0), in LowerSETCC()
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