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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/msa/
Dtest_dlsa.s4 # CHECK: dlsa $8, $9, $10, 1 # encoding: [0x01,0x2a,0x40,0x15]
5 # CHECK: dlsa $8, $9, $10, 2 # encoding: [0x01,0x2a,0x40,0x55]
6 # CHECK: dlsa $8, $9, $10, 3 # encoding: [0x01,0x2a,0x40,0x95]
7 # CHECK: dlsa $8, $9, $10, 4 # encoding: [0x01,0x2a,0x40,0xd5]
9 dlsa $8, $9, $10, 1
10 dlsa $8, $9, $10, 2
11 dlsa $8, $9, $10, 3
12 dlsa $8, $9, $10, 4
Dinvalid-64.s8 dlsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
9 dlsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
/external/llvm/test/MC/Mips/msa/
Dtest_dlsa.s4 # CHECK: dlsa $8, $9, $10, 1 # encoding: [0x01,0x2a,0x40,0x15]
5 # CHECK: dlsa $8, $9, $10, 2 # encoding: [0x01,0x2a,0x40,0x55]
6 # CHECK: dlsa $8, $9, $10, 3 # encoding: [0x01,0x2a,0x40,0x95]
7 # CHECK: dlsa $8, $9, $10, 4 # encoding: [0x01,0x2a,0x40,0xd5]
9 dlsa $8, $9, $10, 1
10 dlsa $8, $9, $10, 2
11 dlsa $8, $9, $10, 3
12 dlsa $8, $9, $10, 4
Dinvalid-64.s8 dlsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
9 dlsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
/external/llvm/test/MC/Disassembler/Mips/msa/
Dtest_dlsa.txt3 0x01 0x2a 0x40 0x15 # CHECK: dlsa $8, $9, $10, 1
4 0x01 0x2a 0x40 0x55 # CHECK: dlsa $8, $9, $10, 2
5 0x01 0x2a 0x40 0x95 # CHECK: dlsa $8, $9, $10, 3
6 0x01 0x2a 0x40 0xd5 # CHECK: dlsa $8, $9, $10, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/msa/
Dtest_dlsa.txt3 0x01 0x2a 0x40 0x15 # CHECK: dlsa $8, $9, $10, 1
4 0x01 0x2a 0x40 0x55 # CHECK: dlsa $8, $9, $10, 2
5 0x01 0x2a 0x40 0x95 # CHECK: dlsa $8, $9, $10, 3
6 0x01 0x2a 0x40 0xd5 # CHECK: dlsa $8, $9, $10, 4
/external/llvm/test/CodeGen/Mips/msa/
Dspecial.ll37 %0 = tail call i64 @llvm.mips.dlsa(i64 %a, i64 %b, i32 2)
41 declare i64 @llvm.mips.dlsa(i64, i64, i32) nounwind
44 ; MIPS64: dlsa {{\$[0-9]+}}, $5, $4, 2
55 ; MIPS64: dlsa {{\$[0-9]+}}, $5, $4, 2
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/
Dspecial.ll37 %0 = tail call i64 @llvm.mips.dlsa(i64 %a, i64 %b, i32 2)
41 declare i64 @llvm.mips.dlsa(i64, i64, i32) nounwind
44 ; MIPS64: dlsa {{\$[0-9]+}}, $5, $4, 2
55 ; MIPS64: dlsa {{\$[0-9]+}}, $5, $4, 2
/external/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td66 class DLSA_R6_DESC : LSA_R6_DESC_BASE<"dlsa", GPR64Opnd, uimm2_plus1, II_DLSA>;
DMipsMSAInstrInfo.td2332 class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd, II_DLSA>;
/external/llvm/test/MC/Disassembler/Mips/mips64r6/
Dvalid-mips64r6-el.txt109 0xd5 0x10 0x64 0x00 # CHECK: dlsa $2, $3, $4, 4
Dvalid-mips64r6.txt22 0x00 0x64 0x10 0xd5 # CHECK: dlsa $2, $3, $4, 4
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td68 class DLSA_R6_DESC : LSA_R6_DESC_BASE<"dlsa", GPR64Opnd, uimm2_plus1, II_DLSA>;
DMipsMSAInstrInfo.td2335 class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd, II_DLSA>;
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64r6/
Dvalid-mips64r6-el.txt110 0xd5 0x10 0x64 0x00 # CHECK: dlsa $2, $3, $4, 4
Dvalid-mips64r6.txt24 0x00 0x64 0x10 0xd5 # CHECK: dlsa $2, $3, $4, 4
/external/v8/src/mips64/
Dassembler-mips64.h1922 void dlsa(Register rd, Register rt, Register rs, uint8_t sa);
Dassembler-mips64.cc2242 void Assembler::dlsa(Register rd, Register rt, Register rs, uint8_t sa) { in dlsa() function in v8::internal::Assembler
Dmacro-assembler-mips64.cc1092 dlsa(rd, rt, rs, sa - 1); in Dlsa()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenAsmMatcher.inc4896 "div_u.w\004divu\003dla\003dli\004dlsa\005dmfc0\005dmfc1\005dmfc2\006dmf"
5990 …{ 3295 /* dlsa */, Mips::DLSA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUI…
5991 …{ 3295 /* dlsa */, Mips::DLSA_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__Constan…
9139 …{ Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 3295 /* dlsa */, MCK_GPR64AsmReg, 7 /* 0, 1,…
9140 …{ Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3295 /* dlsa */, MCK_GPR64AsmReg, …
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc3148 mips_dlsa, // llvm.mips.dlsa
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen2389 mips_dlsa, // llvm.mips.dlsa
8447 "llvm.mips.dlsa",
16387 1, // llvm.mips.dlsa
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen2389 mips_dlsa, // llvm.mips.dlsa
8447 "llvm.mips.dlsa",
16387 1, // llvm.mips.dlsa
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen2389 mips_dlsa, // llvm.mips.dlsa
8447 "llvm.mips.dlsa",
16387 1, // llvm.mips.dlsa
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen2383 mips_dlsa, // llvm.mips.dlsa
8407 "llvm.mips.dlsa",
16292 1, // llvm.mips.dlsa

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