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Searched refs:dmuh (Results 1 – 15 of 15) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dmips64muldiv.ll33 ; GPR: dmuh $[[T1:[0-9]+]], $4, $[[T0]]
/external/llvm/test/CodeGen/Mips/
Dmips64muldiv.ll33 ; GPR: dmuh $[[T1:[0-9]+]], $4, $[[T0]]
/external/llvm/lib/Target/Mips/
DMicroMips64r6InstrInfo.td47 class DMUH_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmuh", 0b001011000>;
204 class DMUH_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmuh", GPR64Opnd, II_DMUH,
DMips64r6InstrInfo.td69 class DMUH_DESC : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, II_DMUH, mulhs>;
/external/llvm/test/MC/Mips/micromips64r6/
Dvalid.s267 dmuh $3, $4, $5 # CHECK dmuh $3, $4, $5 # encoding: [0x58,0xa4,0x18,0x58]
/external/llvm/test/MC/Disassembler/Mips/mips64r6/
Dvalid-mips64r6-el.txt114 0xdc 0x10 0x64 0x00 # CHECK: dmuh $2, $3, $4
Dvalid-mips64r6.txt27 0x00 0x64 0x10 0xdc # CHECK: dmuh $2, $3, $4
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td71 class DMUH_DESC : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, II_DMUH, mulhs>;
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64r6/
Dvalid-mips64r6-el.txt115 0xdc 0x10 0x64 0x00 # CHECK: dmuh $2, $3, $4
Dvalid-mips64r6.txt29 0x00 0x64 0x10 0xdc # CHECK: dmuh $2, $3, $4
/external/llvm/test/MC/Disassembler/Mips/micromips64r6/
Dvalid.txt263 0x58 0xa4 0x18 0x58 # CHECK: dmuh $3, $4, $5
/external/v8/src/mips64/
Dmacro-assembler-mips64.cc543 dmuh(rd, rs, rt.rm()); in Dmulh()
555 dmuh(rd, rs, scratch); in Dmulh()
Dassembler-mips64.h860 void dmuh(Register rd, Register rs, Register rt);
Dassembler-mips64.cc1944 void Assembler::dmuh(Register rd, Register rs, Register rt) { in dmuh() function in v8::internal::Assembler
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenAsmMatcher.inc6012 …{ 3365 /* dmuh */, Mips::DMUH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_Ha…
9174 …{ Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3365 /* dmuh */, MCK_GPR64AsmReg, …