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Searched refs:dtcr (Results 1 – 16 of 16) sorted by relevance

/external/u-boot/board/ti/ks2_evm/
Dddr3_k2g.c33 .dtcr = 0x710035C7ul,
73 .dtcr = 0x710035C7ul,
134 .dtcr = 0x710035C7ul,
Dddr3_cfg.c31 .dtcr = 0x710035C7ul,
/external/u-boot/arch/arm/mach-keystone/include/mach/
Dddr3.h31 unsigned int dtcr; member
/external/u-boot/arch/arm/mach-sunxi/
Ddram_sun8i_a33.c185 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24); in mctl_data_train_cfg()
187 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24); in mctl_data_train_cfg()
Ddram_sun8i_a83t.c217 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24); in mctl_data_train_cfg()
219 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24); in mctl_data_train_cfg()
Ddram_sunxi_dw.c500 clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, in mctl_channel_init()
532 clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24); in mctl_channel_init()
Ddram_sun8i_a23.c138 writel(0x01000081, &mctl_phy->dtcr); in mctl_init()
Ddram_sun9i.c689 &mctl_phy->dtcr); in mctl_channel_init()
/external/u-boot/arch/arm/include/asm/arch-sunxi/
Ddram_sun8i_a33.h103 u32 dtcr; /* 0xc0 */ member
Ddram_sunxi_dw.h104 u32 dtcr; /* 0xc0 */ member
Ddram_sun8i_a83t.h103 u32 dtcr; /* 0xc0 */ member
Ddram_sun9i.h112 u32 dtcr; /* 0xb0 data training configuration register */ member
Ddram_sun8i_a23.h189 u32 dtcr; /* 0x68 */ member
/external/u-boot/arch/arm/mach-keystone/
Dddr3_spd.c37 debug_ddr_cfg("dtcr 0x%08X\n", ptr->dtcr); in dump_phy_config()
358 spd_cb->phy_cfg.dtcr = (spd->rank == 2) ? 0x730035C7 : 0x710035C7; in init_ddr3param()
Dddr3.c55 __raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET); in ddr3_init_ddrphy()
/external/u-boot/arch/powerpc/include/asm/
Dimmap_83xx.h405 u32 dtcr; member