Searched refs:dtcr (Results 1 – 16 of 16) sorted by relevance
/external/u-boot/board/ti/ks2_evm/ |
D | ddr3_k2g.c | 33 .dtcr = 0x710035C7ul, 73 .dtcr = 0x710035C7ul, 134 .dtcr = 0x710035C7ul,
|
D | ddr3_cfg.c | 31 .dtcr = 0x710035C7ul,
|
/external/u-boot/arch/arm/mach-keystone/include/mach/ |
D | ddr3.h | 31 unsigned int dtcr; member
|
/external/u-boot/arch/arm/mach-sunxi/ |
D | dram_sun8i_a33.c | 185 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24); in mctl_data_train_cfg() 187 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24); in mctl_data_train_cfg()
|
D | dram_sun8i_a83t.c | 217 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24); in mctl_data_train_cfg() 219 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24); in mctl_data_train_cfg()
|
D | dram_sunxi_dw.c | 500 clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, in mctl_channel_init() 532 clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24); in mctl_channel_init()
|
D | dram_sun8i_a23.c | 138 writel(0x01000081, &mctl_phy->dtcr); in mctl_init()
|
D | dram_sun9i.c | 689 &mctl_phy->dtcr); in mctl_channel_init()
|
/external/u-boot/arch/arm/include/asm/arch-sunxi/ |
D | dram_sun8i_a33.h | 103 u32 dtcr; /* 0xc0 */ member
|
D | dram_sunxi_dw.h | 104 u32 dtcr; /* 0xc0 */ member
|
D | dram_sun8i_a83t.h | 103 u32 dtcr; /* 0xc0 */ member
|
D | dram_sun9i.h | 112 u32 dtcr; /* 0xb0 data training configuration register */ member
|
D | dram_sun8i_a23.h | 189 u32 dtcr; /* 0x68 */ member
|
/external/u-boot/arch/arm/mach-keystone/ |
D | ddr3_spd.c | 37 debug_ddr_cfg("dtcr 0x%08X\n", ptr->dtcr); in dump_phy_config() 358 spd_cb->phy_cfg.dtcr = (spd->rank == 2) ? 0x730035C7 : 0x710035C7; in init_ddr3param()
|
D | ddr3.c | 55 __raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET); in ddr3_init_ddrphy()
|
/external/u-boot/arch/powerpc/include/asm/ |
D | immap_83xx.h | 405 u32 dtcr; member
|