Searched refs:dtpr0 (Results 1 – 16 of 16) sorted by relevance
| /external/u-boot/board/ti/ks2_evm/ |
| D | ddr3_k2g.c | 27 .dtpr0 = 0x550F6644ul,
67 .dtpr0 = 0x6D147744ul,
128 .dtpr0 = 0x550E6644ul,
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| D | ddr3_cfg.c | 25 .dtpr0 = 0x9D5CBB66ul,
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| /external/u-boot/arch/arm/mach-keystone/include/mach/ |
| D | ddr3.h | 25 unsigned int dtpr0; member
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| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| D | sdram.h | 82 u32 dtpr0; member
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| /external/u-boot/drivers/ram/stm32mp1/ |
| D | stm32mp1_ddr.h | 134 u32 dtpr0; member
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| D | stm32mp1_ddr_regs.h | 154 u32 dtpr0; /* 0x34 DRAM Timing Parameters0*/ member
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| D | stm32mp1_ddr.c | 143 DDRPHY_REG_TIMING(dtpr0),
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| /external/u-boot/arch/arm/mach-keystone/ |
| D | ddr3_spd.c | 31 debug_ddr_cfg("dtpr0 0x%08X\n", ptr->dtpr0); in dump_phy_config()
325 spd_cb->phy_cfg.dtpr0 = (spd->t_rc & 0x3f) << 26 | in init_ddr3param()
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| D | ddr3.c | 49 __raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET); in ddr3_init_ddrphy()
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| /external/u-boot/arch/arm/include/asm/arch-sunxi/ |
| D | dram_sun8i_a23.h | 181 u32 dtpr0; /* 0x48 dram timing parameters register 0 */ member
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| D | dram_sun6i.h | 170 u32 dtpr0; /* 0x34 dram timing parameters register 0 */ member
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| /external/u-boot/arch/arm/mach-sunxi/ |
| D | dram_sun8i_a23.c | 135 writel(dram_para.tpr3, &mctl_phy->dtpr0); in mctl_init()
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| D | dram_sun6i.c | 136 &mctl_phy->dtpr0); in mctl_channel_init()
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| /external/u-boot/doc/device-tree-bindings/clock/ |
| D | rockchip,rk3288-dmc.txt | 89 dtpr0
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| /external/u-boot/drivers/ram/rockchip/ |
| D | sdram_rk3188.c | 266 copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, in phy_cfg()
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| D | sdram_rk3288.c | 300 copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, in phy_cfg()
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