Home
last modified time | relevance | path

Searched refs:elt1 (Results 1 – 25 of 43) sorted by relevance

12

/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/
DDerivedTypes.h235 create(StringRef Name, Type *elt1, Tys *... elts) { in create() argument
236 assert(elt1 && "Cannot create a struct type with no elements with this"); in create()
237 SmallVector<llvm::Type *, 8> StructFields({elt1, elts...}); in create()
254 get(Type *elt1, Tys *... elts) { in get() argument
255 assert(elt1 && "Cannot create a struct type with no elements with this"); in get()
256 LLVMContext &Ctx = elt1->getContext(); in get()
257 SmallVector<llvm::Type *, 8> StructFields({elt1, elts...}); in get()
291 setBody(Type *elt1, Tys *... elts) { in setBody() argument
292 assert(elt1 && "Cannot create a struct type with no elements with this"); in setBody()
293 SmallVector<llvm::Type *, 8> StructFields({elt1, elts...}); in setBody()
/external/llvm/test/CodeGen/AMDGPU/
Dsign_extend.ll87 %elt1 = extractelement <4 x i32> %ext, i32 1
91 store volatile i32 %elt1, i32 addrspace(1)* %out
113 %elt1 = extractelement <4 x i32> %ext, i32 1
117 store volatile i32 %elt1, i32 addrspace(1)* %out
134 %elt1 = extractelement <4 x i32> %ext, i32 1
138 store volatile i32 %elt1, i32 addrspace(1)* %out
157 %elt1 = extractelement <4 x i32> %ext, i32 1
161 store volatile i32 %elt1, i32 addrspace(1)* %out
Dextract-vector-elt-build-vector-combine.ll21 %elt1 = load volatile i32, i32 addrspace(1)* %in
26 %vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
63 %elt1 = load volatile i32, i32 addrspace(1)* %in
68 %vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
107 %elt1 = load volatile i32, i32 addrspace(1)* %in
112 %vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
Dpartially-dead-super-register-immediate.ll21 %elt1 = extractelement <2 x i32> %vec, i32 1
23 store i32 %elt1, i32 addrspace(1)* %out
Dextract_vector_elt-i64.ll14 %elt1 = extractelement <2 x i32> %vec, i32 1
17 store volatile i32 %elt1, i32 addrspace(1)* %out
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dextract-vector-elt-build-vector-combine.ll21 %elt1 = load volatile i32, i32 addrspace(1)* %in
26 %vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
63 %elt1 = load volatile i32, i32 addrspace(1)* %in
68 %vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
107 %elt1 = load volatile i32, i32 addrspace(1)* %in
112 %vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
Dsign_extend.ll138 %elt1 = extractelement <4 x i32> %ext, i32 1
142 store volatile i32 %elt1, i32 addrspace(1)* %out
171 %elt1 = extractelement <4 x i32> %ext, i32 1
175 store volatile i32 %elt1, i32 addrspace(1)* %out
197 %elt1 = extractelement <4 x i32> %ext, i32 1
201 store volatile i32 %elt1, i32 addrspace(1)* %out
218 %elt1 = extractelement <4 x i32> %ext, i32 1
222 store volatile i32 %elt1, i32 addrspace(1)* %out
Dpacked-op-sel.ll281 …%vec2.fneg.elt1.broadcast = shufflevector <2 x half> %vec2.fneg, <2 x half> undef, <2 x i32> <i32 …
283 …2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %vec2.fneg.elt1.broadcast)
308 %vec2.elt1 = extractelement <2 x half> %vec2, i32 1
309 %neg.vec2.elt1 = fsub half -0.0, %vec2.elt1
311 %neg.vec2.elt1.insert = insertelement <2 x half> %vec2, half %neg.vec2.elt1, i32 1
312 …ll <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %neg.vec2.elt1.insert)
334 %vec1.elt1.broadcast = shufflevector <2 x i16> %vec1, <2 x i16> undef, <2 x i32> <i32 1, i32 1>
335 %result = add <2 x i16> %vec0, %vec1.elt1.broadcast
361 %vec2.elt1.broadcast = shufflevector <2 x half> %vec2, <2 x half> undef, <2 x i32> <i32 1, i32 1>
363 …all <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %vec2.elt1.broadcast)
[all …]
Dpartially-dead-super-register-immediate.ll21 %elt1 = extractelement <2 x i32> %vec, i32 1
23 store i32 %elt1, i32 addrspace(1)* %out
Dextract_vector_elt-i8.ll207 %elt1 = extractelement <8 x i8> %load, i32 1
211 store volatile i8 %elt1, i8 addrspace(1)* undef, align 1
226 %elt1 = extractelement <8 x i8> %load, i32 1
230 store volatile i8 %elt1, i8 addrspace(1)* undef, align 1
261 %elt1 = extractelement <16 x i8> %load, i32 1
265 store volatile i8 %elt1, i8 addrspace(1)* undef, align 1
Dfneg.f16.ll142 %elt1 = extractelement <2 x half> %fneg, i32 1
145 %fadd1 = fadd half %elt1, 2.0
160 %elt1 = extractelement <2 x half> %fneg, i32 1
162 store volatile half %elt1, half addrspace(1)* undef
Dextract_vector_elt-i64.ll14 %elt1 = extractelement <2 x i32> %vec, i32 1
17 store volatile i32 %elt1, i32 addrspace(1)* %out
Dfabs.f16.ll171 %elt1 = extractelement <2 x half> %fabs, i32 1
174 %fadd1 = fadd half %elt1, 2.0
195 %elt1 = extractelement <2 x half> %fabs, i32 1
197 store volatile half %elt1, half addrspace(1)* undef
Dds_read2_superreg.ll51 %elt1 = extractelement <4 x float> %val0, i32 1
56 %add1 = fadd float %elt1, %elt3
76 %elt1 = extractelement <3 x float> %val0, i32 1
80 %add1 = fadd float %add0, %elt1
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/ValueTracking/
Dsignbits-extract-elt.ll5 ; then instsimplify will know that %elt1 is non-negative at icmp.
11 %elt1 = extractelement <2 x i32> %vec, i32 1
12 %bool = icmp slt i32 %elt1, 0
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/AMDGPU/
Dreduction.ll28 %elt1 = extractelement <4 x half> %a, i64 1
32 %add1 = fadd fast half %elt1, %elt0
72 %elt1 = extractelement <8 x half> %vec8, i64 1
80 %add1 = fadd fast half %elt1, %elt0
142 %elt1 = extractelement <16 x half> %vec16, i64 1
158 %add1 = fadd fast half %elt1, %elt0
192 %elt1 = extractelement <4 x half> %a, i64 1
196 %add1 = fsub fast half %elt1, %elt0
226 %elt1 = extractelement <4 x i16> %a, i64 1
230 %add1 = add i16 %elt1, %elt0
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dvec-shift-07.ll148 %elt1 = extractelement <16 x i8> %val, i32 15
150 %ext1 = sext i8 %elt1 to i64
162 %elt1 = extractelement <16 x i16> %val, i32 7
164 %ext1 = sext i16 %elt1 to i64
176 %elt1 = extractelement <16 x i32> %val, i32 3
178 %ext1 = sext i32 %elt1 to i64
Dvec-perm-12.ll34 %elt1 = extractelement <4 x i32> %x, i32 2
38 %vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
/external/llvm/test/CodeGen/SystemZ/
Dvec-shift-07.ll148 %elt1 = extractelement <16 x i8> %val, i32 15
150 %ext1 = sext i8 %elt1 to i64
162 %elt1 = extractelement <16 x i16> %val, i32 7
164 %ext1 = sext i16 %elt1 to i64
176 %elt1 = extractelement <16 x i32> %val, i32 3
178 %ext1 = sext i32 %elt1 to i64
Dvec-perm-12.ll34 %elt1 = extractelement <4 x i32> %x, i32 2
38 %vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SPARC/
Dvector-extract-elt.ll15 %elt1 = extractelement <4 x i32> %vec4, i32 1
16 %sum = add i32 %elt0, %elt1
/external/swiftshader/third_party/subzero/tests_lit/assembler/x86/
Dopcode_register_encodings.ll173 define internal <4 x i32> @test_pinsrd(<4 x i32> %vec, i32 %elt1, i32 %elt2,
176 %elt12 = add i32 %elt1, %elt2
180 %res3 = insertelement <4 x i32> %res2, i32 %elt1, i32 3
191 %elt1 = trunc i32 %elt1_w to i8
195 %elt12 = add i8 %elt1, %elt2
199 %res3 = insertelement <16 x i8> %res2, i8 %elt1, i32 15
210 %elt1 = trunc i32 %elt1_w to i16
214 %elt12 = add i16 %elt1, %elt2
218 %res3 = insertelement <8 x i16> %res2, i16 %elt1, i32 7
/external/swiftshader/third_party/LLVM/include/llvm/
DDerivedTypes.h225 static StructType *create(StringRef Name, Type *elt1, ...) END_WITH_NULL;
240 static StructType *get(Type *elt1, ...) END_WITH_NULL;
267 void setBody(Type *elt1, ...) END_WITH_NULL;
/external/swiftshader/third_party/llvm-subzero/include/llvm/IR/
DDerivedTypes.h231 static StructType *create(StringRef Name, Type *elt1, ...) LLVM_END_WITH_NULL;
243 static StructType *get(Type *elt1, ...) LLVM_END_WITH_NULL;
272 void setBody(Type *elt1, ...) LLVM_END_WITH_NULL;
/external/llvm/include/llvm/IR/
DDerivedTypes.h226 static StructType *create(StringRef Name, Type *elt1, ...) LLVM_END_WITH_NULL;
238 static StructType *get(Type *elt1, ...) LLVM_END_WITH_NULL;
267 void setBody(Type *elt1, ...) LLVM_END_WITH_NULL;

12