1; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=kaveri -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,CIVI %s 2; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,CIVI,GFX89 %s 3; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,GFX9 %s 4 5; FIXME: Should be able to do scalar op 6; GCN-LABEL: {{^}}s_fneg_f16: 7define amdgpu_kernel void @s_fneg_f16(half addrspace(1)* %out, half %in) #0 { 8 %fneg = fsub half -0.0, %in 9 store half %fneg, half addrspace(1)* %out 10 ret void 11} 12 13; FIXME: Should be able to use bit operations when illegal type as 14; well. 15 16; GCN-LABEL: {{^}}v_fneg_f16: 17; GCN: {{flat|global}}_load_ushort [[VAL:v[0-9]+]], 18; GCN: v_xor_b32_e32 [[XOR:v[0-9]+]], 0x8000, [[VAL]] 19; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[XOR]] 20; SI: buffer_store_short [[XOR]] 21define amdgpu_kernel void @v_fneg_f16(half addrspace(1)* %out, half addrspace(1)* %in) #0 { 22 %tid = call i32 @llvm.amdgcn.workitem.id.x() 23 %gep.in = getelementptr inbounds half, half addrspace(1)* %in, i32 %tid 24 %gep.out = getelementptr inbounds half, half addrspace(1)* %in, i32 %tid 25 %val = load half, half addrspace(1)* %gep.in, align 2 26 %fneg = fsub half -0.0, %val 27 store half %fneg, half addrspace(1)* %gep.out 28 ret void 29} 30 31; GCN-LABEL: {{^}}s_fneg_free_f16: 32; GCN: s_load_dword [[NEG_VALUE:s[0-9]+]], 33; GCN: s_xor_b32 [[XOR:s[0-9]+]], [[NEG_VALUE]], 0x8000{{$}} 34; GCN: v_mov_b32_e32 [[V_XOR:v[0-9]+]], [[XOR]] 35; GCN: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[V_XOR]] 36define amdgpu_kernel void @s_fneg_free_f16(half addrspace(1)* %out, i16 %in) #0 { 37 %bc = bitcast i16 %in to half 38 %fsub = fsub half -0.0, %bc 39 store half %fsub, half addrspace(1)* %out 40 ret void 41} 42 43; GCN-LABEL: {{^}}v_fneg_fold_f16: 44; GCN: {{flat|global}}_load_ushort [[NEG_VALUE:v[0-9]+]] 45 46; CI-DAG: v_cvt_f32_f16_e32 [[CVT_VAL:v[0-9]+]], [[NEG_VALUE]] 47; CI-DAG: v_cvt_f32_f16_e64 [[NEG_CVT0:v[0-9]+]], -[[NEG_VALUE]] 48; CI: v_mul_f32_e32 [[MUL:v[0-9]+]], [[NEG_CVT0]], [[CVT_VAL]] 49; CI: v_cvt_f16_f32_e32 [[CVT1:v[0-9]+]], [[MUL]] 50; CI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[CVT1]] 51 52; VI-NOT: [[NEG_VALUE]] 53; VI: v_mul_f16_e64 v{{[0-9]+}}, -[[NEG_VALUE]], [[NEG_VALUE]] 54define amdgpu_kernel void @v_fneg_fold_f16(half addrspace(1)* %out, half addrspace(1)* %in) #0 { 55 %val = load half, half addrspace(1)* %in 56 %fsub = fsub half -0.0, %val 57 %fmul = fmul half %fsub, %val 58 store half %fmul, half addrspace(1)* %out 59 ret void 60} 61 62; GCN-LABEL: {{^}}s_fneg_v2f16: 63; GCN: s_xor_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80008000 64define amdgpu_kernel void @s_fneg_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %in) #0 { 65 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %in 66 store <2 x half> %fneg, <2 x half> addrspace(1)* %out 67 ret void 68} 69 70; GCN-LABEL: {{^}}s_fneg_v2f16_nonload: 71; GCN: s_xor_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80008000 72define amdgpu_kernel void @s_fneg_v2f16_nonload(<2 x half> addrspace(1)* %out) #0 { 73 %in = call i32 asm sideeffect "; def $0", "=s"() 74 %in.bc = bitcast i32 %in to <2 x half> 75 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %in.bc 76 store <2 x half> %fneg, <2 x half> addrspace(1)* %out 77 ret void 78} 79 80; GCN-LABEL: {{^}}v_fneg_v2f16: 81; GCN: {{flat|global}}_load_dword [[VAL:v[0-9]+]] 82; GCN: v_xor_b32_e32 v{{[0-9]+}}, 0x80008000, [[VAL]] 83define amdgpu_kernel void @v_fneg_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 { 84 %tid = call i32 @llvm.amdgcn.workitem.id.x() 85 %gep.in = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i32 %tid 86 %gep.out = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i32 %tid 87 %val = load <2 x half>, <2 x half> addrspace(1)* %gep.in, align 2 88 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %val 89 store <2 x half> %fneg, <2 x half> addrspace(1)* %gep.out 90 ret void 91} 92 93; GCN-LABEL: {{^}}fneg_free_v2f16: 94; GCN: s_load_dword [[VAL:s[0-9]+]] 95; GCN: s_xor_b32 s{{[0-9]+}}, [[VAL]], 0x80008000 96define amdgpu_kernel void @fneg_free_v2f16(<2 x half> addrspace(1)* %out, i32 %in) #0 { 97 %bc = bitcast i32 %in to <2 x half> 98 %fsub = fsub <2 x half> <half -0.0, half -0.0>, %bc 99 store <2 x half> %fsub, <2 x half> addrspace(1)* %out 100 ret void 101} 102 103; GCN-LABEL: {{^}}v_fneg_fold_v2f16: 104; GCN: {{flat|global}}_load_dword [[VAL:v[0-9]+]] 105 106; CI: v_xor_b32_e32 [[FNEG:v[0-9]+]], 0x80008000, [[VAL]] 107; CI: v_lshrrev_b32_e32 108; CI: v_lshrrev_b32_e32 109 110; CI: v_cvt_f32_f16_e32 v{{[0-9]+}}, v{{[0-9]+}} 111; CI: v_cvt_f32_f16_e32 v{{[0-9]+}}, v{{[0-9]+}} 112; CI: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 113; CI: v_cvt_f16_f32 114; CI: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 115; CI: v_cvt_f16_f32 116 117; VI: v_mul_f16_sdwa v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 118; VI: v_mul_f16_e64 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}} 119 120; GFX9: v_pk_mul_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} neg_lo:[1,0] neg_hi:[1,0]{{$}} 121define amdgpu_kernel void @v_fneg_fold_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 { 122 %val = load <2 x half>, <2 x half> addrspace(1)* %in 123 %fsub = fsub <2 x half> <half -0.0, half -0.0>, %val 124 %fmul = fmul <2 x half> %fsub, %val 125 store <2 x half> %fmul, <2 x half> addrspace(1)* %out 126 ret void 127} 128 129; GCN-LABEL: {{^}}v_extract_fneg_fold_v2f16: 130; GCN-DAG: {{flat|global}}_load_dword [[VAL:v[0-9]+]] 131; CI-DAG: v_mul_f32_e32 v{{[0-9]+}}, -4.0, v{{[0-9]+}} 132; CI-DAG: v_sub_f32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}} 133 134; GFX89-DAG: v_mul_f16_e32 v{{[0-9]+}}, -4.0, [[VAL]] 135; GFX89-DAG: v_mov_b32_e32 [[CONST2:v[0-9]+]], 0x4000 136; GFX89-DAG: v_sub_f16_sdwa v{{[0-9]+}}, [[CONST2]], [[VAL]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 137 138define amdgpu_kernel void @v_extract_fneg_fold_v2f16(<2 x half> addrspace(1)* %in) #0 { 139 %val = load <2 x half>, <2 x half> addrspace(1)* %in 140 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %val 141 %elt0 = extractelement <2 x half> %fneg, i32 0 142 %elt1 = extractelement <2 x half> %fneg, i32 1 143 144 %fmul0 = fmul half %elt0, 4.0 145 %fadd1 = fadd half %elt1, 2.0 146 store volatile half %fmul0, half addrspace(1)* undef 147 store volatile half %fadd1, half addrspace(1)* undef 148 ret void 149} 150 151; GCN-LABEL: {{^}}v_extract_fneg_no_fold_v2f16: 152; GCN: {{flat|global}}_load_dword [[VAL:v[0-9]+]] 153; GCN: v_xor_b32_e32 [[NEG:v[0-9]+]], 0x80008000, [[VAL]] 154; CIVI: v_lshrrev_b32_e32 [[ELT1:v[0-9]+]], 16, [[NEG]] 155; GFX9: global_store_short_d16_hi v{{\[[0-9]+:[0-9]+\]}}, [[NEG]], off 156define amdgpu_kernel void @v_extract_fneg_no_fold_v2f16(<2 x half> addrspace(1)* %in) #0 { 157 %val = load <2 x half>, <2 x half> addrspace(1)* %in 158 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %val 159 %elt0 = extractelement <2 x half> %fneg, i32 0 160 %elt1 = extractelement <2 x half> %fneg, i32 1 161 store volatile half %elt0, half addrspace(1)* undef 162 store volatile half %elt1, half addrspace(1)* undef 163 ret void 164} 165 166declare i32 @llvm.amdgcn.workitem.id.x() #1 167 168attributes #0 = { nounwind } 169attributes #1 = { nounwind readnone } 170