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Searched refs:exec_hi (Results 1 – 25 of 27) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dsmem-err.s15 s_store_dword exec_hi, s[2:3], 0x0
27 s_buffer_store_dword exec_hi, s[0:3], 0x0
39 s_load_dword exec_hi, s[0:1], s4
51 s_buffer_load_dword exec_hi, s[0:3], s4
Dgfx7_asm_all.s10473 s_mov_b32 exec_hi, s1
10512 s_mov_b32 s5, exec_hi
10641 s_cmov_b32 exec_hi, s1
10680 s_cmov_b32 s5, exec_hi
10809 s_not_b32 exec_hi, s1
10848 s_not_b32 s5, exec_hi
10977 s_wqm_b32 exec_hi, s1
11016 s_wqm_b32 s5, exec_hi
11145 s_brev_b32 exec_hi, s1
11184 s_brev_b32 s5, exec_hi
[all …]
Dgfx9_asm_all.s11527 s_mov_b32 exec_hi, s1
11551 s_mov_b32 s5, exec_hi
11647 s_cmov_b32 exec_hi, s1
11671 s_cmov_b32 s5, exec_hi
11767 s_not_b32 exec_hi, s1
11791 s_not_b32 s5, exec_hi
11887 s_wqm_b32 exec_hi, s1
11911 s_wqm_b32 s5, exec_hi
12007 s_brev_b32 exec_hi, s1
12031 s_brev_b32 s5, exec_hi
[all …]
Dvop-err.s27 v_movreld_b32 v0, exec_hi
108 v_cndmask_b32 v0, exec_hi, v2, vcc
168 v_addc_u32 v0, vcc, exec_hi, v0, vcc
220 v_madak_f32 v0, exec_hi, v0, 0x11213141
Dgfx8_asm_all.s11088 s_mov_b32 exec_hi, s1
11127 s_mov_b32 s5, exec_hi
11256 s_cmov_b32 exec_hi, s1
11295 s_cmov_b32 s5, exec_hi
11424 s_not_b32 exec_hi, s1
11463 s_not_b32 s5, exec_hi
11592 s_wqm_b32 exec_hi, s1
11631 s_wqm_b32 s5, exec_hi
11760 s_brev_b32 exec_hi, s1
11799 s_brev_b32 s5, exec_hi
[all …]
Dflat-gfx9.s112 flat_load_dword v1, v[3:4], exec_hi
115 flat_store_dword v[3:4], v1, exec_hi
Dflat-scratch-instructions.s123 scratch_load_dword v1, off, exec_hi
127 scratch_store_dword off, v2, exec_hi
Ddl-insts.s30 v_fmac_f32 v5, exec_hi, v2
69 v_fmac_f32_e64 v5, exec_hi, v2
97 v_fmac_f32_e64 v5, v1, exec_hi
215 v_xnor_b32 v5, exec_hi, v2
254 v_xnor_b32_e64 v5, exec_hi, v2
282 v_xnor_b32_e64 v5, v1, exec_hi
315 v_xnor_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
Dreg-syntax-extra.s26 s_mov_b64 [exec_lo,exec_hi], s[2:3]
Dflat-global.s123 global_load_dword v1, v[3:4], exec_hi
/external/llvm/test/CodeGen/AMDGPU/
Dread_register.ll19 ; CHECK: v_mov_b32_e32 v[[HI:[0-9]+]], exec_hi
65 ; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], exec_hi
68 %exec_hi = call i32 @llvm.read_register.i32(metadata !6)
69 store i32 %exec_hi, i32 addrspace(1)* %out
81 !6 = !{!"exec_hi"}
Dwrite_register.ll64 ; CHECK: s_mov_b32 exec_hi, 0
65 ; CHECK: s_mov_b32 exec_hi, s{{[0-9]+}}
80 !6 = !{!"exec_hi"}
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dread_register.ll21 ; CHECK: v_mov_b32_e32 v[[HI:[0-9]+]], exec_hi
67 ; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], exec_hi
70 %exec_hi = call i32 @llvm.read_register.i32(metadata !6)
71 store i32 %exec_hi, i32 addrspace(1)* %out
83 !6 = !{!"exec_hi"}
Dwrite_register.ll70 ; CHECK: s_mov_b32 exec_hi, 0
71 ; CHECK: s_mov_b32 exec_hi, s{{[0-9]+}}
90 !6 = !{!"exec_hi"}
/external/llvm/test/MC/AMDGPU/
Dreg-syntax-extra.s26 s_mov_b64 [exec_lo,exec_hi], s[2:3]
/external/mesa3d/src/amd/common/
Dac_debug.c776 uint32_t pc_hi, pc_lo, exec_hi, exec_lo; in ac_get_wave_info() local
784 &w->inst_dw1, &exec_hi, &exec_lo) == 12) { in ac_get_wave_info()
786 w->exec = ((uint64_t)exec_hi << 32) | exec_lo; in ac_get_wave_info()
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dgfx9_dasm_all.txt9156 # CHECK: s_mov_b32 exec_hi, s1 ; encoding: [0x01,0x00,0xff,0xbe]
9180 # CHECK: s_mov_b32 s5, exec_hi ; encoding: [0x7f,0x00,0x85,0xbe]
9276 # CHECK: s_cmov_b32 exec_hi, s1 ; encoding: [0x01,0x02,0xff,0xbe]
9300 # CHECK: s_cmov_b32 s5, exec_hi ; encoding: [0x7f,0x02,0x85,0xbe]
9396 # CHECK: s_not_b32 exec_hi, s1 ; encoding: [0x01,0x04,0xff,0xbe]
9420 # CHECK: s_not_b32 s5, exec_hi ; encoding: [0x7f,0x04,0x85,0xbe]
9516 # CHECK: s_wqm_b32 exec_hi, s1 ; encoding: [0x01,0x06,0xff,0xbe]
9540 # CHECK: s_wqm_b32 s5, exec_hi ; encoding: [0x7f,0x06,0x85,0xbe]
9636 # CHECK: s_brev_b32 exec_hi, s1 ; encoding: [0x01,0x08,0xff,0xbe]
9660 # CHECK: s_brev_b32 s5, exec_hi ; encoding: [0x7f,0x08,0x85,0xbe]
[all …]
Dvop3_gfx9.txt228 # GFX9: v_mad_mix_f32 v5, exec_hi, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x7f,0x04,0x0e,0x04]
258 # GFX9: v_mad_mix_f32 v5, v1, exec_hi, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xff,0x0c,0x04]
288 # GFX9: v_mad_mix_f32 v5, v1, v2, exec_hi ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xfe,0x01]
375 # GFX9: v_mad_mixhi_f16 v5, exec_hi, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x7f,0x04,0x0e,0x04]
405 # GFX9: v_mad_mixhi_f16 v5, v1, exec_hi, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xff,0x0c,0x04]
435 # GFX9: v_mad_mixhi_f16 v5, v1, v2, exec_hi ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xfe,0x01]
522 # GFX9: v_mad_mixlo_f16 v5, exec_hi, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x7f,0x04,0x0e,0x04]
552 # GFX9: v_mad_mixlo_f16 v5, v1, exec_hi, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xff,0x0c,0x04]
582 # GFX9: v_mad_mixlo_f16 v5, v1, v2, exec_hi ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xfe,0x01]
Dvop1.txt66 # CHECK: v_ceil_f32_e32 v123, exec_hi ; encoding: [0x7f,0x3a,0xf6,0x7e]
156 # CHECK: v_cvt_f64_i32_e32 v[222:223], exec_hi ; encoding: [0x7f,0x08,0xbc,0x7f]
Dgfx8_dasm_all.txt7824 # CHECK: s_mov_b32 exec_hi, s1 ; encoding: [0x01,0x00,0xff,0xbe]
7863 # CHECK: s_mov_b32 s5, exec_hi ; encoding: [0x7f,0x00,0x85,0xbe]
7992 # CHECK: s_cmov_b32 exec_hi, s1 ; encoding: [0x01,0x02,0xff,0xbe]
8031 # CHECK: s_cmov_b32 s5, exec_hi ; encoding: [0x7f,0x02,0x85,0xbe]
8160 # CHECK: s_not_b32 exec_hi, s1 ; encoding: [0x01,0x04,0xff,0xbe]
8199 # CHECK: s_not_b32 s5, exec_hi ; encoding: [0x7f,0x04,0x85,0xbe]
8328 # CHECK: s_wqm_b32 exec_hi, s1 ; encoding: [0x01,0x06,0xff,0xbe]
8367 # CHECK: s_wqm_b32 s5, exec_hi ; encoding: [0x7f,0x06,0x85,0xbe]
8496 # CHECK: s_brev_b32 exec_hi, s1 ; encoding: [0x01,0x08,0xff,0xbe]
8535 # CHECK: s_brev_b32 s5, exec_hi ; encoding: [0x7f,0x08,0x85,0xbe]
[all …]
Ddl-insts.txt36 # CHECK: v_fmac_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x76]
93 # CHECK: v_fmac_f32_e64 v5, exec_hi, v2 ; encoding: [0x05,0x00,0x3b,0xd1,0x7f,0x04,0x02,0x00]
135 # CHECK: v_fmac_f32_e64 v5, v1, exec_hi ; encoding: [0x05,0x00,0x3b,0xd1,0x01,0xff,0x00,0x00]
309 # CHECK: v_xnor_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x7a]
366 # CHECK: v_xnor_b32_e64 v5, exec_hi, v2 ; encoding: [0x05,0x00,0x3d,0xd1,0x7f,0x04,0x02,0x00]
408 # CHECK: v_xnor_b32_e64 v5, v1, exec_hi ; encoding: [0x05,0x00,0x3d,0xd1,0x01,0xff,0x00,0x00]
456 # CHECK: v_xnor_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_se…
/external/llvm/test/MC/Disassembler/AMDGPU/
Dvop1.txt66 # CHECK: v_ceil_f32_e32 v123, exec_hi ; encoding: [0x7f,0x3a,0xf6,0x7e]
156 # CHECK: v_cvt_f64_i32_e32 v[222:223], exec_hi ; encoding: [0x7f,0x08,0xbc,0x7f]
/external/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td35 def EXEC_HI : SIReg<"exec_hi", 127>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td62 def EXEC_HI : SIReg<"exec_hi", 127>;
DSMInstructions.td251 // FIXME: exec_lo/exec_hi appear to be allowed for SMRD loads on

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