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1; RUN: llc -march=amdgcn -mcpu=bonaire -enable-misched=0 -verify-machineinstrs < %s | FileCheck %s
2
3declare void @llvm.write_register.i32(metadata, i32) #0
4declare void @llvm.write_register.i64(metadata, i64) #0
5
6; CHECK-LABEL: {{^}}test_write_m0:
7define amdgpu_kernel void @test_write_m0(i32 %val) #0 {
8  call void @llvm.write_register.i32(metadata !0, i32 0)
9  call void @llvm.write_register.i32(metadata !0, i32 -1)
10  call void @llvm.write_register.i32(metadata !0, i32 %val)
11  call void @llvm.amdgcn.wave.barrier() #1
12  ret void
13}
14
15; CHECK-LABEL: {{^}}test_write_exec:
16; CHECK: s_mov_b64 exec, 0
17; CHECK: s_mov_b64 exec, -1
18; CHECK: s_mov_b64 exec, s{{\[[0-9]+:[0-9]+\]}}
19define amdgpu_kernel void @test_write_exec(i64 %val) #0 {
20  call void @llvm.write_register.i64(metadata !1, i64 0)
21  call void @llvm.write_register.i64(metadata !1, i64 -1)
22  call void @llvm.write_register.i64(metadata !1, i64 %val)
23  call void @llvm.amdgcn.wave.barrier() #1
24  ret void
25}
26
27; CHECK-LABEL: {{^}}test_write_flat_scratch:
28; CHECK: s_mov_b64 flat_scratch, 0
29; CHECK: s_mov_b64 flat_scratch, -1
30; CHECK: s_mov_b64 flat_scratch, s{{\[[0-9]+:[0-9]+\]}}
31define amdgpu_kernel void @test_write_flat_scratch(i64 %val) #0 {
32  call void @llvm.write_register.i64(metadata !2, i64 0)
33  call void @llvm.write_register.i64(metadata !2, i64 -1)
34  call void @llvm.write_register.i64(metadata !2, i64 %val)
35  call void @llvm.amdgcn.wave.barrier() #1
36  ret void
37}
38
39; CHECK-LABEL: {{^}}test_write_flat_scratch_lo:
40; CHECK: s_mov_b32 flat_scratch_lo, 0
41; CHECK: s_mov_b32 flat_scratch_lo, s{{[0-9]+}}
42define amdgpu_kernel void @test_write_flat_scratch_lo(i32 %val) #0 {
43  call void @llvm.write_register.i32(metadata !3, i32 0)
44  call void @llvm.write_register.i32(metadata !3, i32 %val)
45  call void @llvm.amdgcn.wave.barrier() #1
46  ret void
47}
48
49; CHECK-LABEL: {{^}}test_write_flat_scratch_hi:
50; CHECK: s_mov_b32 flat_scratch_hi, 0
51; CHECK: s_mov_b32 flat_scratch_hi, s{{[0-9]+}}
52define amdgpu_kernel void @test_write_flat_scratch_hi(i32 %val) #0 {
53  call void @llvm.write_register.i32(metadata !4, i32 0)
54  call void @llvm.write_register.i32(metadata !4, i32 %val)
55  call void @llvm.amdgcn.wave.barrier() #1
56  ret void
57}
58
59; CHECK-LABEL: {{^}}test_write_exec_lo:
60; CHECK: s_mov_b32 exec_lo, 0
61; CHECK: s_mov_b32 exec_lo, s{{[0-9]+}}
62define amdgpu_kernel void @test_write_exec_lo(i32 %val) #0 {
63  call void @llvm.write_register.i32(metadata !5, i32 0)
64  call void @llvm.write_register.i32(metadata !5, i32 %val)
65  call void @llvm.amdgcn.wave.barrier() #1
66  ret void
67}
68
69; CHECK-LABEL: {{^}}test_write_exec_hi:
70; CHECK: s_mov_b32 exec_hi, 0
71; CHECK: s_mov_b32 exec_hi, s{{[0-9]+}}
72define amdgpu_kernel void @test_write_exec_hi(i32 %val) #0 {
73  call void @llvm.write_register.i32(metadata !6, i32 0)
74  call void @llvm.write_register.i32(metadata !6, i32 %val)
75  call void @llvm.amdgcn.wave.barrier() #1
76  ret void
77}
78
79declare void @llvm.amdgcn.wave.barrier() #1
80
81attributes #0 = { nounwind }
82attributes #1 = { convergent nounwind }
83
84!0 = !{!"m0"}
85!1 = !{!"exec"}
86!2 = !{!"flat_scratch"}
87!3 = !{!"flat_scratch_lo"}
88!4 = !{!"flat_scratch_hi"}
89!5 = !{!"exec_lo"}
90!6 = !{!"exec_hi"}
91