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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dsmem-err.s12 s_store_dword exec_lo, s[2:3], 0x0
24 s_buffer_store_dword exec_lo, s[0:3], 0x0
36 s_load_dword exec_lo, s[0:1], s4
48 s_buffer_load_dword exec_lo, s[0:3], s4
Dgfx7_asm_all.s10470 s_mov_b32 exec_lo, s1
10509 s_mov_b32 s5, exec_lo
10638 s_cmov_b32 exec_lo, s1
10677 s_cmov_b32 s5, exec_lo
10806 s_not_b32 exec_lo, s1
10845 s_not_b32 s5, exec_lo
10974 s_wqm_b32 exec_lo, s1
11013 s_wqm_b32 s5, exec_lo
11142 s_brev_b32 exec_lo, s1
11181 s_brev_b32 s5, exec_lo
[all …]
Dgfx9_asm_all.s11524 s_mov_b32 exec_lo, s1
11548 s_mov_b32 s5, exec_lo
11644 s_cmov_b32 exec_lo, s1
11668 s_cmov_b32 s5, exec_lo
11764 s_not_b32 exec_lo, s1
11788 s_not_b32 s5, exec_lo
11884 s_wqm_b32 exec_lo, s1
11908 s_wqm_b32 s5, exec_lo
12004 s_brev_b32 exec_lo, s1
12028 s_brev_b32 s5, exec_lo
[all …]
Dvop-err.s24 v_movreld_b32 v0, exec_lo
105 v_cndmask_b32 v0, exec_lo, v2, vcc
165 v_addc_u32 v0, vcc, exec_lo, v0, vcc
217 v_madak_f32 v0, exec_lo, v0, 0x11213141
Dgfx8_asm_all.s11085 s_mov_b32 exec_lo, s1
11124 s_mov_b32 s5, exec_lo
11253 s_cmov_b32 exec_lo, s1
11292 s_cmov_b32 s5, exec_lo
11421 s_not_b32 exec_lo, s1
11460 s_not_b32 s5, exec_lo
11589 s_wqm_b32 exec_lo, s1
11628 s_wqm_b32 s5, exec_lo
11757 s_brev_b32 exec_lo, s1
11796 s_brev_b32 s5, exec_lo
[all …]
Dflat-scratch-instructions.s131 scratch_load_dword v1, off, exec_lo
135 scratch_store_dword off, v2, exec_lo
Ddl-insts.s28 v_fmac_f32 v5, exec_lo, v2
67 v_fmac_f32_e64 v5, exec_lo, v2
95 v_fmac_f32_e64 v5, v1, exec_lo
213 v_xnor_b32 v5, exec_lo, v2
252 v_xnor_b32_e64 v5, exec_lo, v2
280 v_xnor_b32_e64 v5, v1, exec_lo
313 v_xnor_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
Dreg-syntax-extra.s26 s_mov_b64 [exec_lo,exec_hi], s[2:3]
/external/llvm/test/CodeGen/AMDGPU/
Dread_register.ll18 ; CHECK: v_mov_b32_e32 v[[LO:[0-9]+]], exec_lo
56 ; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], exec_lo
59 %exec_lo = call i32 @llvm.read_register.i32(metadata !5)
60 store i32 %exec_lo, i32 addrspace(1)* %out
80 !5 = !{!"exec_lo"}
Dwrite_register.ll55 ; CHECK: s_mov_b32 exec_lo, 0
56 ; CHECK: s_mov_b32 exec_lo, s{{[0-9]+}}
79 !5 = !{!"exec_lo"}
Dwrite-register-vgpr-into-sgpr.ll22 !0 = !{!"exec_lo"}
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dread_register.ll20 ; CHECK: v_mov_b32_e32 v[[LO:[0-9]+]], exec_lo
58 ; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], exec_lo
61 %exec_lo = call i32 @llvm.read_register.i32(metadata !5)
62 store i32 %exec_lo, i32 addrspace(1)* %out
82 !5 = !{!"exec_lo"}
Dwrite_register.ll60 ; CHECK: s_mov_b32 exec_lo, 0
61 ; CHECK: s_mov_b32 exec_lo, s{{[0-9]+}}
89 !5 = !{!"exec_lo"}
Dwrite-register-vgpr-into-sgpr.ll24 !0 = !{!"exec_lo"}
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dmov.txt18 # CHECK: v_mov_b32_e32 v199, exec_lo ; encoding: [0x7e,0x02,0x8e,0x7f]
Dvop1.txt24 # CHECK: v_mov_b32_e32 v199, exec_lo ; encoding: [0x7e,0x02,0x8e,0x7f]
63 # CHECK: v_trunc_f32_e32 v123, exec_lo ; encoding: [0x7e,0x38,0xf6,0x7e]
189 # CHECK: v_cvt_i16_f16_e32 v123, exec_lo ; encoding: [0x7e,0x78,0xf6,0x7e]
Dgfx9_dasm_all.txt9153 # CHECK: s_mov_b32 exec_lo, s1 ; encoding: [0x01,0x00,0xfe,0xbe]
9177 # CHECK: s_mov_b32 s5, exec_lo ; encoding: [0x7e,0x00,0x85,0xbe]
9273 # CHECK: s_cmov_b32 exec_lo, s1 ; encoding: [0x01,0x02,0xfe,0xbe]
9297 # CHECK: s_cmov_b32 s5, exec_lo ; encoding: [0x7e,0x02,0x85,0xbe]
9393 # CHECK: s_not_b32 exec_lo, s1 ; encoding: [0x01,0x04,0xfe,0xbe]
9417 # CHECK: s_not_b32 s5, exec_lo ; encoding: [0x7e,0x04,0x85,0xbe]
9513 # CHECK: s_wqm_b32 exec_lo, s1 ; encoding: [0x01,0x06,0xfe,0xbe]
9537 # CHECK: s_wqm_b32 s5, exec_lo ; encoding: [0x7e,0x06,0x85,0xbe]
9633 # CHECK: s_brev_b32 exec_lo, s1 ; encoding: [0x01,0x08,0xfe,0xbe]
9657 # CHECK: s_brev_b32 s5, exec_lo ; encoding: [0x7e,0x08,0x85,0xbe]
[all …]
Dvop3_gfx9.txt225 # GFX9: v_mad_mix_f32 v5, exec_lo, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x7e,0x04,0x0e,0x04]
255 # GFX9: v_mad_mix_f32 v5, v1, exec_lo, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xfd,0x0c,0x04]
285 # GFX9: v_mad_mix_f32 v5, v1, v2, exec_lo ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xfa,0x01]
372 # GFX9: v_mad_mixhi_f16 v5, exec_lo, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x7e,0x04,0x0e,0x04]
402 # GFX9: v_mad_mixhi_f16 v5, v1, exec_lo, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xfd,0x0c,0x04]
432 # GFX9: v_mad_mixhi_f16 v5, v1, v2, exec_lo ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xfa,0x01]
519 # GFX9: v_mad_mixlo_f16 v5, exec_lo, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x7e,0x04,0x0e,0x04]
549 # GFX9: v_mad_mixlo_f16 v5, v1, exec_lo, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xfd,0x0c,0x04]
579 # GFX9: v_mad_mixlo_f16 v5, v1, v2, exec_lo ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xfa,0x01]
Dgfx8_dasm_all.txt7821 # CHECK: s_mov_b32 exec_lo, s1 ; encoding: [0x01,0x00,0xfe,0xbe]
7860 # CHECK: s_mov_b32 s5, exec_lo ; encoding: [0x7e,0x00,0x85,0xbe]
7989 # CHECK: s_cmov_b32 exec_lo, s1 ; encoding: [0x01,0x02,0xfe,0xbe]
8028 # CHECK: s_cmov_b32 s5, exec_lo ; encoding: [0x7e,0x02,0x85,0xbe]
8157 # CHECK: s_not_b32 exec_lo, s1 ; encoding: [0x01,0x04,0xfe,0xbe]
8196 # CHECK: s_not_b32 s5, exec_lo ; encoding: [0x7e,0x04,0x85,0xbe]
8325 # CHECK: s_wqm_b32 exec_lo, s1 ; encoding: [0x01,0x06,0xfe,0xbe]
8364 # CHECK: s_wqm_b32 s5, exec_lo ; encoding: [0x7e,0x06,0x85,0xbe]
8493 # CHECK: s_brev_b32 exec_lo, s1 ; encoding: [0x01,0x08,0xfe,0xbe]
8532 # CHECK: s_brev_b32 s5, exec_lo ; encoding: [0x7e,0x08,0x85,0xbe]
[all …]
Ddl-insts.txt33 # CHECK: v_fmac_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x76]
90 # CHECK: v_fmac_f32_e64 v5, exec_lo, v2 ; encoding: [0x05,0x00,0x3b,0xd1,0x7e,0x04,0x02,0x00]
132 # CHECK: v_fmac_f32_e64 v5, v1, exec_lo ; encoding: [0x05,0x00,0x3b,0xd1,0x01,0xfd,0x00,0x00]
306 # CHECK: v_xnor_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x7a]
363 # CHECK: v_xnor_b32_e64 v5, exec_lo, v2 ; encoding: [0x05,0x00,0x3d,0xd1,0x7e,0x04,0x02,0x00]
405 # CHECK: v_xnor_b32_e64 v5, v1, exec_lo ; encoding: [0x05,0x00,0x3d,0xd1,0x01,0xfd,0x00,0x00]
453 # CHECK: v_xnor_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_se…
/external/llvm/test/MC/Disassembler/AMDGPU/
Dmov.txt18 # CHECK: v_mov_b32_e32 v199, exec_lo ; encoding: [0x7e,0x02,0x8e,0x7f]
Dvop1.txt24 # CHECK: v_mov_b32_e32 v199, exec_lo ; encoding: [0x7e,0x02,0x8e,0x7f]
63 # CHECK: v_trunc_f32_e32 v123, exec_lo ; encoding: [0x7e,0x38,0xf6,0x7e]
189 # CHECK: v_cvt_i16_f16_e32 v123, exec_lo ; encoding: [0x7e,0x78,0xf6,0x7e]
/external/llvm/test/MC/AMDGPU/
Dreg-syntax-extra.s26 s_mov_b64 [exec_lo,exec_hi], s[2:3]
/external/mesa3d/src/amd/common/
Dac_debug.c776 uint32_t pc_hi, pc_lo, exec_hi, exec_lo; in ac_get_wave_info() local
784 &w->inst_dw1, &exec_hi, &exec_lo) == 12) { in ac_get_wave_info()
786 w->exec = ((uint64_t)exec_hi << 32) | exec_lo; in ac_get_wave_info()
/external/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td34 def EXEC_LO : SIReg<"exec_lo", 126>;

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