fcvt (reference) in projects: external - OpenGrok search results

Project(s)

Full Search
Definition
Symbol
File Path
History
Type

Searched refs:fcvt (Results 1 – 25 of 92) sorted by relevance

12 3 4

/external/llvm/test/CodeGen/AArch64/
D	fp16-v8-instructions.ll	`6 ; CHECK: fcvt 7 ; CHECK: fcvt 9 ; CHECK-DAG: fcvt 10 ; CHECK-DAG: fcvt 12 ; CHECK-DAG: fcvt 13 ; CHECK-DAG: fcvt 15 ; CHECK-DAG: fcvt 16 ; CHECK-DAG: fcvt 18 ; CHECK-DAG: fcvt 19 ; CHECK-DAG: fcvt [all …]`
D	fp16-v4-instructions.ll	`86 ; CHECK-DAG: fcvt 87 ; CHECK-DAG: fcvt 88 ; CHECK-DAG: fcvt 89 ; CHECK-DAG: fcvt 107 ; CHECK-DAG: fcvt 108 ; CHECK-DAG: fcvt 109 ; CHECK-DAG: fcvt 110 ; CHECK-DAG: fcvt 272 ; CHECK-DAG: fcvt 273 ; CHECK-DAG: fcvt [all …]`
D	f16-instructions.ll	`6 ; CHECK-NEXT: fcvt s1, h1 7 ; CHECK-NEXT: fcvt s0, h0 9 ; CHECK-NEXT: fcvt h0, s0 17 ; CHECK-NEXT: fcvt s1, h1 18 ; CHECK-NEXT: fcvt s0, h0 20 ; CHECK-NEXT: fcvt h0, s0 28 ; CHECK-NEXT: fcvt s1, h1 29 ; CHECK-NEXT: fcvt s0, h0 31 ; CHECK-NEXT: fcvt h0, s0 39 ; CHECK-NEXT: fcvt s1, h1 [all …]`
D	f16-convert.ll	`6 ; CHECK-NEXT: fcvt s0, [[HREG]] 17 ; CHECK-NEXT: fcvt d0, [[HREG]] 28 ; CHECK-NEXT: fcvt s0, [[HREG]] 41 ; CHECK-NEXT: fcvt d0, [[HREG]] 54 ; CHECK-NEXT: fcvt s0, [[HREG]] 66 ; CHECK-NEXT: fcvt d0, [[HREG]] 78 ; CHECK-NEXT: fcvt s0, [[HREG]] 90 ; CHECK-NEXT: fcvt d0, [[HREG]] 102 ; CHECK-NEXT: fcvt s0, [[HREG]] 114 ; CHECK-NEXT: fcvt d0, [[HREG]] [all …]`
D	arm64-fast-isel-conversion-fallback.ll	`7 ; CHECK: fcvt s1, h0 18 ; CHECK: fcvt s1, h0 31 ; CHECK: fcvt h0, s0 42 ; CHECK: fcvt h0, s0 53 ; CHECK: fcvt h0, s0 63 ; CHECK: fcvt h0, s0 73 ; CHECK: fcvt h0, s0 84 ; CHECK: fcvt h0, s0 95 ; CHECK: fcvt h0, s0 106 ; CHECK: fcvt h0, s0 [all …]`
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
D	fp16-v8-instructions.ll	`7 ; CHECK-CVT: fcvt 8 ; CHECK-CVT: fcvt 10 ; CHECK-CVT-DAG: fcvt 11 ; CHECK-CVT-DAG: fcvt 13 ; CHECK-CVT-DAG: fcvt 14 ; CHECK-CVT-DAG: fcvt 16 ; CHECK-CVT-DAG: fcvt 17 ; CHECK-CVT-DAG: fcvt 19 ; CHECK-CVT-DAG: fcvt 20 ; CHECK-CVT-DAG: fcvt [all …]`
D	f16-instructions.ll	`7 ; CHECK-CVT-NEXT: fcvt s1, h1 8 ; CHECK-CVT-NEXT: fcvt s0, h0 10 ; CHECK-CVT-NEXT: fcvt h0, s0 23 ; CHECK-CVT-NEXT: fcvt s1, h1 24 ; CHECK-CVT-NEXT: fcvt s0, h0 26 ; CHECK-CVT-NEXT: fcvt h0, s0 39 ; CHECK-CVT-NEXT: fcvt s1, h1 40 ; CHECK-CVT-NEXT: fcvt s0, h0 42 ; CHECK-CVT-NEXT: fcvt h0, s0 55 ; CHECK-CVT-NEXT: fcvt s1, h1 [all …]`
D	f16-convert.ll	`6 ; CHECK-NEXT: fcvt s0, [[HREG]] 17 ; CHECK-NEXT: fcvt d0, [[HREG]] 28 ; CHECK-NEXT: fcvt s0, [[HREG]] 41 ; CHECK-NEXT: fcvt d0, [[HREG]] 54 ; CHECK-NEXT: fcvt s0, [[HREG]] 66 ; CHECK-NEXT: fcvt d0, [[HREG]] 78 ; CHECK-NEXT: fcvt s0, [[HREG]] 90 ; CHECK-NEXT: fcvt d0, [[HREG]] 102 ; CHECK-NEXT: fcvt s0, [[HREG]] 114 ; CHECK-NEXT: fcvt d0, [[HREG]] [all …]`
D	arm64-fast-isel-conversion-fallback.ll	`7 ; CHECK: fcvt s1, h0 18 ; CHECK: fcvt s1, h0 31 ; CHECK: fcvt h0, s0 42 ; CHECK: fcvt h0, s0 53 ; CHECK: fcvt h0, s0 63 ; CHECK: fcvt h0, s0 73 ; CHECK: fcvt h0, s0 84 ; CHECK: fcvt h0, s0 95 ; CHECK: fcvt h0, s0 106 ; CHECK: fcvt h0, s0 [all …]`
D	fp16_intrinsic_scalar_1op.ll	146 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtas.i32.f16(half %a) 147 %0 = trunc i32 %fcvt to i16 165 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtau.i32.f16(half %a) 166 %0 = trunc i32 %fcvt to i16 184 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtms.i32.f16(half %a) 185 %0 = trunc i32 %fcvt to i16 203 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtmu.i32.f16(half %a) 204 %0 = trunc i32 %fcvt to i16 222 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtns.i32.f16(half %a) 223 %0 = trunc i32 %fcvt to i16 [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/RISCV/
D	rv64f-valid.s	`9 # CHECK-INST: fcvt.l.s a0, ft0, dyn 12 fcvt.l.s a0, ft0, dyn 13 # CHECK-INST: fcvt.lu.s a1, ft1, dyn 16 fcvt.lu.s a1, ft1, dyn 17 # CHECK-INST: fcvt.s.l ft2, a2, dyn 20 fcvt.s.l ft2, a2, dyn 21 # CHECK-INST: fcvt.s.lu ft3, a3, dyn 24 fcvt.s.lu ft3, a3, dyn 27 # CHECK-INST: fcvt.l.s a4, ft4, rne 29 fcvt.l.s a4, ft4, rne [all …]`
D	rv64d-valid.s	`9 # CHECK-INST: fcvt.l.d a0, ft0, dyn 12 fcvt.l.d a0, ft0, dyn 13 # CHECK-INST: fcvt.lu.d a1, ft1, dyn 16 fcvt.lu.d a1, ft1, dyn 21 # CHECK-INST: fcvt.d.l ft3, a3, dyn 24 fcvt.d.l ft3, a3, dyn 25 # CHECK-INST: fcvt.d.lu ft4, a4, dyn 28 fcvt.d.lu ft4, a4, dyn 35 # CHECK-INST: fcvt.d.l ft3, a3, rne 38 fcvt.d.l ft3, a3, rne [all …]`
D	rv64f-aliases-valid.s	`16 # CHECK-INST: fcvt.l.s a0, ft0, dyn 17 # CHECK-ALIAS: fcvt.l.s a0, ft0{{[[:space:]]}} 18 fcvt.l.s a0, ft0 19 # CHECK-INST: fcvt.lu.s a1, ft1, dyn 20 # CHECK-ALIAS: fcvt.lu.s a1, ft1{{[[:space:]]}} 21 fcvt.lu.s a1, ft1 22 # CHECK-INST: fcvt.s.l ft2, a2, dyn 23 # CHECK-ALIAS: fcvt.s.l ft2, a2{{[[:space:]]}} 24 fcvt.s.l ft2, a2 25 # CHECK-INST: fcvt.s.lu ft3, a3, dyn [all …]`
D	rv64d-aliases-valid.s	`16 # CHECK-INST: fcvt.l.d a0, ft0, dyn 17 # CHECK-ALIAS: fcvt.l.d a0, ft0{{[[:space:]]}} 18 fcvt.l.d a0, ft0 19 # CHECK-INST: fcvt.lu.d a1, ft1, dyn 20 # CHECK-ALIAS: fcvt.lu.d a1, ft1{{[[:space:]]}} 21 fcvt.lu.d a1, ft1 22 # CHECK-INST: fcvt.d.l ft3, a3, dyn 23 # CHECK-ALIAS: fcvt.d.l ft3, a3{{[[:space:]]}} 24 fcvt.d.l ft3, a3 25 # CHECK-INST: fcvt.d.lu ft4, a4, dyn [all …]`
D	rv32d-valid.s	`93 # CHECK-INST: fcvt.s.d fs5, fs6, dyn 95 fcvt.s.d fs5, fs6, dyn 96 # CHECK-INST: fcvt.d.s fs7, fs8 98 fcvt.d.s fs7, fs8 112 # CHECK-INST: fcvt.w.d a4, ft11, dyn 114 fcvt.w.d a4, ft11, dyn 115 # CHECK-INST: fcvt.d.w ft0, a5 117 fcvt.d.w ft0, a5 118 # CHECK-INST: fcvt.d.wu ft1, a6 120 fcvt.d.wu ft1, a6 [all …]`
D	rv32f-valid.s	`87 # CHECK-INST: fcvt.w.s a0, fs5, dyn 89 fcvt.w.s a0, fs5, dyn 90 # CHECK-INST: fcvt.wu.s a1, fs6, dyn 92 fcvt.wu.s a1, fs6, dyn 108 # CHECK-INST: fcvt.s.w ft11, a4, dyn 110 fcvt.s.w ft11, a4, dyn 111 # CHECK-INST: fcvt.s.wu ft0, a5, dyn 113 fcvt.s.wu ft0, a5, dyn 155 # CHECK-INST: fcvt.w.s a0, fs5, rup 157 fcvt.w.s a0, fs5, rup [all …]`
D	rvf-aliases-valid.s	`128 # CHECK-INST: fcvt.w.s a0, fs5, dyn 129 # CHECK-ALIAS: fcvt.w.s a0, fs5{{[[:space:]]}} 130 fcvt.w.s a0, fs5 131 # CHECK-INST: fcvt.wu.s a1, fs6, dyn 132 # CHECK-ALIAS: fcvt.wu.s a1, fs6{{[[:space:]]}} 133 fcvt.wu.s a1, fs6 134 # CHECK-INST: fcvt.s.w ft11, a4, dyn 135 # CHECK-ALIAS: fcvt.s.w ft11, a4{{[[:space:]]}} 136 fcvt.s.w ft11, a4 137 # CHECK-INST: fcvt.s.wu ft0, a5, dyn [all …]`
D	rvd-aliases-valid.s	`77 # CHECK-INST: fcvt.s.d fs5, fs6, dyn 78 # CHECK-ALIAS: fcvt.s.d fs5, fs6{{[[:space:]]}} 79 fcvt.s.d fs5, fs6 80 # CHECK-INST: fcvt.w.d a4, ft11, dyn 81 # CHECK-ALIAS: fcvt.w.d a4, ft11{{[[:space:]]}} 82 fcvt.w.d a4, ft11 83 # CHECK-INST: fcvt.wu.d a5, ft10, dyn 84 # CHECK-ALIAS: fcvt.wu.d a5, ft10{{[[:space:]]}} 85 fcvt.wu.d a5, ft10`
D	rv64f-invalid.s	`4 fcvt.l.s ft0, a0 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction 5 fcvt.lu.s ft1, a1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction 8 fcvt.s.l a2, ft2 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction 9 fcvt.s.lu a3, ft3 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction`
D	rv64d-invalid.s	`4 fcvt.l.d ft0, a0 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction 5 fcvt.lu.d ft1, a1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction 9 fcvt.d.l a3, ft3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction 10 fcvt.d.lu a4, ft4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction`
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/
D	fcvt.s	`10 fcvt z0.h, p0/m, z0.s label 16 fcvt z0.h, p0/m, z0.d label 22 fcvt z0.s, p0/m, z0.h label 28 fcvt z0.s, p0/m, z0.d label 34 fcvt z0.d, p0/m, z0.h label 40 fcvt z0.d, p0/m, z0.s label 56 fcvt z5.d, p0/m, z0.s label 68 fcvt z5.d, p0/m, z0.s label`
D	fcvt-diagnostics.s	`3 fcvt z0.h, p0/m, z0.h label 8 fcvt z0.s, p0/m, z0.s label 13 fcvt z0.d, p0/m, z0.d label 22 fcvt z0.h, p8/m, z0.s label`
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
D	RISCVInstrInfoD.td	111 def FCVT_S_D : FPUnaryOp_r_frm<0b0100000, FPR32, FPR64, "fcvt.s.d"> { 114 def : FPUnaryOpDynFrmAlias<FCVT_S_D, "fcvt.s.d", FPR32, FPR64>; 116 def FCVT_D_S : FPUnaryOp_r<0b0100001, 0b000, FPR64, FPR32, "fcvt.d.s"> { 128 def FCVT_W_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.w.d"> { 131 def : FPUnaryOpDynFrmAlias<FCVT_W_D, "fcvt.w.d", GPR, FPR64>; 133 def FCVT_WU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.wu.d"> { 136 def : FPUnaryOpDynFrmAlias<FCVT_WU_D, "fcvt.wu.d", GPR, FPR64>; 138 def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.w"> { 142 def FCVT_D_WU : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.wu"> { 148 def FCVT_L_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.l.d"> { [all …]
D	RISCVInstrInfoF.td	132 def FCVT_W_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.w.s"> { 135 def : FPUnaryOpDynFrmAlias<FCVT_W_S, "fcvt.w.s", GPR, FPR32>; 137 def FCVT_WU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.wu.s"> { 140 def : FPUnaryOpDynFrmAlias<FCVT_WU_S, "fcvt.wu.s", GPR, FPR32>; 154 def FCVT_S_W : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.w"> { 157 def : FPUnaryOpDynFrmAlias<FCVT_S_W, "fcvt.s.w", FPR32, GPR>; 159 def FCVT_S_WU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.wu"> { 162 def : FPUnaryOpDynFrmAlias<FCVT_S_WU, "fcvt.s.wu", FPR32, GPR>; 170 def FCVT_L_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.l.s"> { 173 def : FPUnaryOpDynFrmAlias<FCVT_L_S, "fcvt.l.s", GPR, FPR32>; [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/RISCV/
D	double-convert.ll	`12 ; RV32IFD-NEXT: fcvt.s.d ft0, ft0 25 ; RV32IFD-NEXT: fcvt.d.s ft0, ft0 42 ; RV32IFD-NEXT: fcvt.w.d a0, ft0, rtz 56 ; RV32IFD-NEXT: fcvt.wu.d a0, ft0, rtz 67 ; RV32IFD-NEXT: fcvt.d.w ft0, a0 81 ; RV32IFD-NEXT: fcvt.d.wu ft0, a0`

12 3 4

art
bionic
bootable
build
cts
dalvik
developers
development
device
external
frameworks
hardware
kernel
libcore
libnativehelper
packages
pdk
platform_testing
sdk
system
test
toolchain
tools