1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ 3; RUN: | FileCheck -check-prefix=RV32IFD %s 4 5define float @fcvt_s_d(double %a) nounwind { 6; RV32IFD-LABEL: fcvt_s_d: 7; RV32IFD: # %bb.0: 8; RV32IFD-NEXT: addi sp, sp, -16 9; RV32IFD-NEXT: sw a0, 8(sp) 10; RV32IFD-NEXT: sw a1, 12(sp) 11; RV32IFD-NEXT: fld ft0, 8(sp) 12; RV32IFD-NEXT: fcvt.s.d ft0, ft0 13; RV32IFD-NEXT: fmv.x.w a0, ft0 14; RV32IFD-NEXT: addi sp, sp, 16 15; RV32IFD-NEXT: ret 16 %1 = fptrunc double %a to float 17 ret float %1 18} 19 20define double @fcvt_d_s(float %a) nounwind { 21; RV32IFD-LABEL: fcvt_d_s: 22; RV32IFD: # %bb.0: 23; RV32IFD-NEXT: addi sp, sp, -16 24; RV32IFD-NEXT: fmv.w.x ft0, a0 25; RV32IFD-NEXT: fcvt.d.s ft0, ft0 26; RV32IFD-NEXT: fsd ft0, 8(sp) 27; RV32IFD-NEXT: lw a0, 8(sp) 28; RV32IFD-NEXT: lw a1, 12(sp) 29; RV32IFD-NEXT: addi sp, sp, 16 30; RV32IFD-NEXT: ret 31 %1 = fpext float %a to double 32 ret double %1 33} 34 35define i32 @fcvt_w_d(double %a) nounwind { 36; RV32IFD-LABEL: fcvt_w_d: 37; RV32IFD: # %bb.0: 38; RV32IFD-NEXT: addi sp, sp, -16 39; RV32IFD-NEXT: sw a0, 8(sp) 40; RV32IFD-NEXT: sw a1, 12(sp) 41; RV32IFD-NEXT: fld ft0, 8(sp) 42; RV32IFD-NEXT: fcvt.w.d a0, ft0, rtz 43; RV32IFD-NEXT: addi sp, sp, 16 44; RV32IFD-NEXT: ret 45 %1 = fptosi double %a to i32 46 ret i32 %1 47} 48 49define i32 @fcvt_wu_d(double %a) nounwind { 50; RV32IFD-LABEL: fcvt_wu_d: 51; RV32IFD: # %bb.0: 52; RV32IFD-NEXT: addi sp, sp, -16 53; RV32IFD-NEXT: sw a0, 8(sp) 54; RV32IFD-NEXT: sw a1, 12(sp) 55; RV32IFD-NEXT: fld ft0, 8(sp) 56; RV32IFD-NEXT: fcvt.wu.d a0, ft0, rtz 57; RV32IFD-NEXT: addi sp, sp, 16 58; RV32IFD-NEXT: ret 59 %1 = fptoui double %a to i32 60 ret i32 %1 61} 62 63define double @fcvt_d_w(i32 %a) nounwind { 64; RV32IFD-LABEL: fcvt_d_w: 65; RV32IFD: # %bb.0: 66; RV32IFD-NEXT: addi sp, sp, -16 67; RV32IFD-NEXT: fcvt.d.w ft0, a0 68; RV32IFD-NEXT: fsd ft0, 8(sp) 69; RV32IFD-NEXT: lw a0, 8(sp) 70; RV32IFD-NEXT: lw a1, 12(sp) 71; RV32IFD-NEXT: addi sp, sp, 16 72; RV32IFD-NEXT: ret 73 %1 = sitofp i32 %a to double 74 ret double %1 75} 76 77define double @fcvt_d_wu(i32 %a) nounwind { 78; RV32IFD-LABEL: fcvt_d_wu: 79; RV32IFD: # %bb.0: 80; RV32IFD-NEXT: addi sp, sp, -16 81; RV32IFD-NEXT: fcvt.d.wu ft0, a0 82; RV32IFD-NEXT: fsd ft0, 8(sp) 83; RV32IFD-NEXT: lw a0, 8(sp) 84; RV32IFD-NEXT: lw a1, 12(sp) 85; RV32IFD-NEXT: addi sp, sp, 16 86; RV32IFD-NEXT: ret 87 %1 = uitofp i32 %a to double 88 ret double %1 89} 90