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Searched refs:findRegisterDefOperandIdx (Results 1 – 25 of 31) sorted by relevance

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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DMachineInstr.h338 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
345 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
353 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
375 int findRegisterDefOperandIdx(unsigned Reg,
383 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h907 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
914 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
922 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
956 int findRegisterDefOperandIdx(unsigned Reg,
964 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
/external/llvm/lib/CodeGen/
DMachineCombiner.cpp156 DefInstr, DefInstr->findRegisterDefOperandIdx(MO.getReg()), in getDepth()
163 DefInstr, DefInstr->findRegisterDefOperandIdx(MO.getReg()), in getDepth()
205 NewRoot, NewRoot->findRegisterDefOperandIdx(MO.getReg()), UseMO, in getLatency()
DAggressiveAntiDepBreaker.cpp687 int Idx = UseMI->findRegisterDefOperandIdx(NewReg, false, true, TRI); in FindSuitableFreeRegisters()
DTwoAddressInstructionPass.cpp1326 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA); in tryInstructionTransform()
DMachineInstr.cpp1340 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap, in findRegisterDefOperandIdx() function in MachineInstr
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DMachineInstr.h997 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
1004 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
1012 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
1046 int findRegisterDefOperandIdx(unsigned Reg,
1054 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DMachineCombiner.cpp187 int DefIdx = DefInstr->findRegisterDefOperandIdx(MO.getReg()); in getDepth()
196 DefInstr, DefInstr->findRegisterDefOperandIdx(MO.getReg()), in getDepth()
238 NewRoot, NewRoot->findRegisterDefOperandIdx(MO.getReg()), UseMO, in getLatency()
DAggressiveAntiDepBreaker.cpp707 int Idx = UseMI->findRegisterDefOperandIdx(NewReg, false, true, TRI); in FindSuitableFreeRegisters()
DTwoAddressInstructionPass.cpp1381 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA); in tryInstructionTransform()
DMachineInstr.cpp813 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap, in findRegisterDefOperandIdx() function in MachineInstr
/external/llvm/lib/Target/AMDGPU/
DR600EmitClauseMarkers.cpp218 if (UseI != Def && UseI->findRegisterDefOperandIdx(MOI->getReg()) != -1) in canClauseLocalKillFitInClause()
DR600InstrInfo.cpp231 return MI.findRegisterDefOperandIdx(AMDGPU::AR_X) != -1; in definesAddressRegister()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DScheduleDAGInstrs.cpp600 int DefIdx = DefMI->findRegisterDefOperandIdx(Reg); in ComputeOperandLatency()
611 DefIdx = DefMI->findRegisterDefOperandIdx(Reg, false, true, TRI); in ComputeOperandLatency()
DLiveIntervalAnalysis.cpp279 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1; in isPartialRedef()
537 int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,tri_); in handlePhysicalRegisterDef()
DTwoAddressInstructionPass.cpp978 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA); in TryInstructionTransform()
DMachineInstr.cpp946 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap, in findRegisterDefOperandIdx() function in MachineInstr
DRegisterCoalescer.cpp659 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); in RemoveCopyByCommutingDef()
/external/llvm/lib/Target/SystemZ/
DSystemZElimCompare.cpp300 int CCDef = MI.findRegisterDefOperandIdx(SystemZ::CC, false, true, TRI); in adjustCCMasksForInstr()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZElimCompare.cpp381 int CCDef = MI.findRegisterDefOperandIdx(SystemZ::CC, false, true, TRI); in adjustCCMasksForInstr()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp316 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel()
343 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel()
889 int DeadNZCVIdx = CmpInstr.findRegisterDefOperandIdx(AArch64::NZCV, true); in optimizeCompareInstr()
2928 int Cmp_NZCV = Root.findRegisterDefOperandIdx(AArch64::NZCV, true); in getMaddPatterns()
3944 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) != -1) in optimizeCondBranch()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp434 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel()
462 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel()
1315 int DeadNZCVIdx = CmpInstr.findRegisterDefOperandIdx(AArch64::NZCV, true); in optimizeCompareInstr()
3638 int Cmp_NZCV = Root.findRegisterDefOperandIdx(AArch64::NZCV, true); in getMaddPatterns()
4798 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) != -1) in optimizeCondBranch()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600InstrInfo.cpp236 return MI.findRegisterDefOperandIdx(R600::AR_X) != -1; in definesAddressRegister()
/external/llvm/lib/Target/ARM/
DARMBaseInstrInfo.cpp1333 int ImpDefIdx = MI.findRegisterDefOperandIdx(DstRegD); in expandPostRAPseudo()
3451 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI); in getBundledDefMI()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMBaseInstrInfo.cpp1502 int ImpDefIdx = MI.findRegisterDefOperandIdx(DstRegD); in expandPostRAPseudo()
3797 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI); in getBundledDefMI()

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