| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | MachineInstr.h | 309 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
330 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
359 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
366 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
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| /external/llvm/lib/CodeGen/ |
| D | MachineCombiner.cpp | 157 InstrPtr, InstrPtr->findRegisterUseOperandIdx(MO.getReg())); in getDepth()
164 InstrPtr, InstrPtr->findRegisterUseOperandIdx(MO.getReg())); in getDepth()
206 UseMO->findRegisterUseOperandIdx(MO.getReg())); in getLatency()
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| D | StackSlotColoring.cpp | 408 if (NextMI->findRegisterUseOperandIdx(LoadReg, true, nullptr) != -1) { in RemoveDeadStores()
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| D | TwoAddressInstructionPass.cpp | 1327 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB); in tryInstructionTransform()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 877 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
898 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
932 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
939 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 967 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
988 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
1022 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
1029 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | MachineCombiner.cpp | 188 int UseIdx = InstrPtr->findRegisterUseOperandIdx(MO.getReg()); in getDepth()
197 InstrPtr, InstrPtr->findRegisterUseOperandIdx(MO.getReg())); in getDepth()
239 UseMO->findRegisterUseOperandIdx(MO.getReg())); in getLatency()
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| D | StackSlotColoring.cpp | 467 if (NextMI->findRegisterUseOperandIdx(LoadReg, true, nullptr) != -1) { in RemoveDeadStores()
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| D | PeepholeOptimizer.cpp | 1516 unsigned Idx = MI.findRegisterUseOperandIdx(Reg); in findTargetRecurrence()
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| D | TwoAddressInstructionPass.cpp | 1382 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB); in tryInstructionTransform()
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| D | MachineInstr.cpp | 762 int MachineInstr::findRegisterUseOperandIdx( in findRegisterUseOperandIdx() function in MachineInstr
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600EmitClauseMarkers.cpp | 215 if (UseI->findRegisterUseOperandIdx(MOI->getReg())) in canClauseLocalKillFitInClause()
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| D | R600InstrInfo.cpp | 227 return MI.findRegisterUseOperandIdx(AMDGPU::AR_X) != -1; in usesAddressRegister()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | VirtRegRewriter.cpp | 324 if (Prev->findRegisterUseOperandIdx(PhysReg) != -1 || in ComputeReloadLoc()
328 if (Prev->findRegisterUseOperandIdx(*Alias) != -1 || in ComputeReloadLoc()
1460 int Idx = NewMI->findRegisterUseOperandIdx(VirtReg, false); in OptimizeByUnfold()
1544 int UseIdx = DefMI->findRegisterUseOperandIdx(DestReg, false); in CommuteToFoldReload()
1957 MI.findRegisterUseOperandIdx(VirtReg) == -1) { in ProcessUses()
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| D | StackSlotColoring.cpp | 696 if (NextMI->findRegisterUseOperandIdx(LoadReg, true, 0) != -1) { in RemoveDeadStores()
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| D | ScheduleDAGInstrs.cpp | 315 int RegUseIndex = UseMI->findRegisterUseOperandIdx(Reg); in BuildSchedGraph()
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| D | RegisterCoalescer.cpp | 552 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true); in AdjustCopiesBackFrom()
724 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false); in RemoveCopyByCommutingDef()
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| D | LiveIntervalAnalysis.cpp | 1779 int KillOp = KillMI->findRegisterUseOperandIdx(li.reg, true); in addIntervalsForSpills()
2038 int UseIdx = LastUse->findRegisterUseOperandIdx(LI->reg, false); in addIntervalsForSpills()
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| D | TwoAddressInstructionPass.cpp | 979 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB); in TryInstructionTransform()
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| D | MachineInstr.cpp | 893 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, in findRegisterUseOperandIdx() function in MachineInstr
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZElimCompare.cpp | 427 int CCUse = MBBI->findRegisterUseOperandIdx(SystemZ::CC, false, TRI); in fuseCompareOperations()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZElimCompare.cpp | 548 int CCUse = MBBI->findRegisterUseOperandIdx(SystemZ::CC, false, TRI); in fuseCompareOperations()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 609 ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI); in genInstrWithNewOpc()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 419 int Idx = memOps[j].MBBI->findRegisterUseOperandIdx(Reg, true); in MergeOpsUpdate()
503 bool BaseKill = Loc->findRegisterUseOperandIdx(Base, true) != -1; in MergeLDR_STR()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.cpp | 232 return MI.findRegisterUseOperandIdx(R600::AR_X) != -1; in usesAddressRegister()
|