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/external/mesa3d/src/gallium/drivers/r600/
Deg_asm.c224 int eg_bytecode_gds_build(struct r600_bytecode *bc, struct r600_bytecode_gds *gds, unsigned id) in eg_bytecode_gds_build() argument
226 unsigned gds_op = (r600_isa_fetch_opcode(bc->isa->hw_class, gds->op) >> 8) & 0x3f; in eg_bytecode_gds_build()
228 if (gds->op == FETCH_OP_TF_WRITE) { in eg_bytecode_gds_build()
235 S_SQ_MEM_GDS_WORD0_SRC_GPR(gds->src_gpr) | in eg_bytecode_gds_build()
236 S_SQ_MEM_GDS_WORD0_SRC_REL(gds->src_rel) | in eg_bytecode_gds_build()
237 S_SQ_MEM_GDS_WORD0_SRC_SEL_X(gds->src_sel_x) | in eg_bytecode_gds_build()
238 S_SQ_MEM_GDS_WORD0_SRC_SEL_Y(gds->src_sel_y) | in eg_bytecode_gds_build()
239 S_SQ_MEM_GDS_WORD0_SRC_SEL_Z(gds->src_sel_z); in eg_bytecode_gds_build()
241 bc->bytecode[id++] = S_SQ_MEM_GDS_WORD1_DST_GPR(gds->dst_gpr) | in eg_bytecode_gds_build()
242 S_SQ_MEM_GDS_WORD1_DST_REL(gds->dst_rel) | in eg_bytecode_gds_build()
[all …]
Dr600_asm.c61 LIST_INITHEAD(&cf->gds); in r600_bytecode_cf()
97 struct r600_bytecode_gds *gds = CALLOC_STRUCT(r600_bytecode_gds); in r600_bytecode_gds() local
99 if (gds == NULL) in r600_bytecode_gds()
101 LIST_INITHEAD(&gds->list); in r600_bytecode_gds()
102 return gds; in r600_bytecode_gds()
1461 int r600_bytecode_add_gds(struct r600_bytecode *bc, const struct r600_bytecode_gds *gds) in r600_bytecode_add_gds() argument
1468 memcpy(ngds, gds, sizeof(struct r600_bytecode_gds)); in r600_bytecode_add_gds()
1471 if (gds->uav_index_mode) in r600_bytecode_add_gds()
1472 egcm_load_index_reg(bc, gds->uav_index_mode - 1, false); in r600_bytecode_add_gds()
1486 LIST_ADDTAIL(&ngds->list, &bc->cf_last->gds); in r600_bytecode_add_gds()
[all …]
Dr600_asm.h194 struct list_head gds; member
270 int eg_bytecode_gds_build(struct r600_bytecode *bc, struct r600_bytecode_gds *gds, unsigned id);
288 const struct r600_bytecode_gds *gds);
Dr600_gpu_load.c92 UPDATE_COUNTER(gds, GDS_BUSY); in r600_update_mmio_counters()
212 return BUSY_INDEX(rscreen, gds); in busy_index_from_type()
Dr600_shader.c3004 struct r600_bytecode_gds gds; in r600_emit_tess_factor() local
3006 memset(&gds, 0, sizeof(struct r600_bytecode_gds)); in r600_emit_tess_factor()
3007 gds.src_gpr = treg[i / 2]; in r600_emit_tess_factor()
3008 gds.src_sel_x = 2 * (i % 2); in r600_emit_tess_factor()
3009 gds.src_sel_y = 1 + (2 * (i % 2)); in r600_emit_tess_factor()
3010 gds.src_sel_z = 4; in r600_emit_tess_factor()
3011 gds.dst_sel_x = 7; in r600_emit_tess_factor()
3012 gds.dst_sel_y = 7; in r600_emit_tess_factor()
3013 gds.dst_sel_z = 7; in r600_emit_tess_factor()
3014 gds.dst_sel_w = 7; in r600_emit_tess_factor()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DAMDGPUAsmGFX7.rst21 …src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
22 …src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
23 … :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
24 … :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
25 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
26 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
27 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
28 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
29 …src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
30 …src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
[all …]
DAMDGPUAsmGFX8.rst21 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
22 …src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
23 …src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
24 …src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
25 … :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
26 … :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
27 … :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
28 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
29 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
30 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
[all …]
DAMDGPUAsmGFX9.rst21 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
22 …src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
23 …src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
24 …src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
25 … :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
26 … :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
27 … :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
28 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
29 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
30 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
[all …]
/external/llvm/test/MC/AMDGPU/
Dexpressions.s5 .globl gds symbol
13 ds_gws_init v2 gds
17 s_mov_b32 s0, gds
22 s_mov_b32 s0, gds+4
Dds.s133 ds_gws_init v2 gds
137 ds_gws_sema_v v2 gds
141 ds_gws_sema_br v2 gds
145 ds_gws_sema_p v2 gds
149 ds_gws_barrier v2 gds
281 ds_ordered_count v8, v2 gds
Dlabels-branch.s13 s_branch gds
16 gds: label
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dexpressions.s5 .globl gds symbol
13 ds_gws_init v2 gds
17 s_mov_b32 s0, gds
22 s_mov_b32 s0, gds+4
Dds.s22 ds_add_src2_f32 v0 offset:4 gds
150 ds_gws_init v2 gds
154 ds_gws_init v3 offset:12345 gds
158 ds_gws_sema_v gds
162 ds_gws_sema_v offset:257 gds
166 ds_gws_sema_br v2 gds
170 ds_gws_sema_p gds
174 ds_gws_barrier v2 gds
315 ds_ordered_count v8, v2 gds
522 ds_swizzle_b32 v8, v2 gds
Dlabels-branch.s18 s_branch gds
23 gds: label
Dgfx7_asm_all.s21 ds_add_u32 v1, v2 offset:65535 gds
42 ds_sub_u32 v1, v2 offset:65535 gds
63 ds_rsub_u32 v1, v2 offset:65535 gds
84 ds_inc_u32 v1, v2 offset:65535 gds
105 ds_dec_u32 v1, v2 offset:65535 gds
126 ds_min_i32 v1, v2 offset:65535 gds
147 ds_max_i32 v1, v2 offset:65535 gds
168 ds_min_u32 v1, v2 offset:65535 gds
189 ds_max_u32 v1, v2 offset:65535 gds
210 ds_and_b32 v1, v2 offset:65535 gds
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DDSInstructions.td48 bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
68 bits<1> gds;
86 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
87 "$addr, $data0$offset$gds"> {
106 (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
107 "$addr, $data0, $data1"#"$offset"#"$gds"> {
126 offset0:$offset0, offset1:$offset1, gds:$gds),
127 "$addr, $data0, $data1$offset0$offset1$gds"> {
145 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
146 "$vdst, $addr, $data0$offset$gds"> {
[all …]
/external/mesa3d/src/gallium/drivers/r600/sb/
Dsb_bc_dump.cpp454 unsigned gds = n.bc.op_ptr->flags & FF_GDS; in dump() local
455 bool gds_has_ret = gds && n.bc.op >= FETCH_OP_GDS_ADD_RET && in dump()
457 bool show_dst = !gds || (gds && gds_has_ret); in dump()
476 unsigned num_src_comp = gds ? 3 : vtx ? ctx.is_cayman() ? 2 : 1 : 4; in dump()
485 if (!gds) in dump()
488 if (gds) { in dump()
Dsb_bc_parser.cpp649 unsigned gds = flags & FF_GDS; in prepare_fetch_clause() local
650 unsigned num_src = gds ? 2 : vtx ? ctx.vtx_src_num : 4; in prepare_fetch_clause()
654 if (gds) { in prepare_fetch_clause()
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dds_vi.txt84 # VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd9,0x00,0x02,0x00,0x00]
87 # VI: ds_gws_init v3 offset:12345 gds ; encoding: [0x39,0x30,0x33,0xd9,0x00,0x03,0x00,0x00]
90 # VI: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
93 # VI: ds_gws_sema_v offset:257 gds ; encoding: [0x01,0x01,0x35,0xd9,0x00,0x00,0x00,0x00]
96 # VI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x37,0xd9,0x00,0x02,0x00,0x00]
99 # VI: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
102 # VI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x3b,0xd9,0x00,0x02,0x00,0x00]
174 # VI: ds_swizzle_b32 v8, v2 gds ; encoding: [0x00,0x00,0x7b,0xd8,0x02,0x00,0x00,0x08]
327 # VI: ds_add_src2_f32 v0 offset:4 gds ; encoding: [0x04,0x00,0x2b,0xd9,0x00,0x00,0x00,0x00]
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.td545 def gds : NamedOperandBit<"GDS", NamedMatchClass<"GDS">>;
2604 dag ins = (ins VGPR_32:$addr, offset:$offset, gds:$gds),
2605 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
2619 dag ins = (ins VGPR_32:$addr, offset:$offset, gds:$gds),
2620 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
2633 gds:$gds),
2634 string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> {
2646 dag ins = (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
2647 string asm = opName#" $addr, $data0"#"$offset$gds"> {
2661 offset0:$offset0, offset1:$offset1, gds:$gds),
[all …]
DVIInstrFormats.td16 bits<1> gds;
25 let Inst{16} = gds;
DSIInstrFormats.td487 bits<1> gds;
496 let Inst{17} = gds;
/external/mesa3d/src/gallium/drivers/radeon/
Dr600_gpu_load.c89 UPDATE_COUNTER(gds, GDS_BUSY); in r600_update_mmio_counters()
229 return BUSY_INDEX(sscreen, gds); in busy_index_from_type()
Dr600_pipe_common.h330 struct r600_mmio_counter gds; member
/external/llvm/test/MC/Disassembler/AMDGPU/
Dds_vi.txt84 # VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd8,0x02,0x00,0x00,0x00]
87 # VI: ds_gws_sema_v v2 gds ; encoding: [0x00,0x00,0x35,0xd8,0x02,0x00,0x00,0x00]
90 # VI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x37,0xd8,0x02,0x00,0x00,0x00]
93 # VI: ds_gws_sema_p v2 gds ; encoding: [0x00,0x00,0x39,0xd8,0x02,0x00,0x00,0x00]
96 # VI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x3b,0xd8,0x02,0x00,0x00,0x00]
195 # VI: ds_ordered_count v8, v2 gds ; encoding: [0x00,0x00,0x7f,0xd8,0x02,0x00,0x00,0x08]

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