| /external/swiftshader/third_party/llvm-7.0/llvm/unittests/tools/llvm-exegesis/X86/ |
| D | SnippetGeneratorTest.cpp | 80 EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitDefs()[0], llvm::X86::AX); in TEST_F()
81 EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitDefs()[1], llvm::X86::EFLAGS); in TEST_F()
101 EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitDefs()[0], llvm::X86::EFLAGS); in TEST_F()
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| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCInstrDesc.h | 233 const unsigned *getImplicitDefs() const { in getImplicitDefs() function
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 497 const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; } in getImplicitDefs() function
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 539 const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; } in getImplicitDefs() function
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 688 bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0; in EmitMachineNode()
757 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()]; in EmitMachineNode()
773 if (const unsigned *IDList = II.getImplicitDefs()) { in EmitMachineNode()
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| D | ScheduleDAGRRList.cpp | 1030 for (const unsigned *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT()
2632 = TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs(); in canClobberReachingPhysRegUse()
2664 const unsigned *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs(); in canClobberPhysRegDefs()
2671 TII->get(SUNode->getMachineOpcode()).getImplicitDefs(); in canClobberPhysRegDefs()
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| D | ScheduleDAGFast.cpp | 428 for (const unsigned *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT()
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| D | ScheduleDAGSDNodes.cpp | 408 TII->get(N->getMachineOpcode()).getImplicitDefs()) { in AddSchedEdges()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 772 bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr; in EmitMachineNode()
838 unsigned Reg = II.getImplicitDefs()[i - NumDefs]; in EmitMachineNode()
873 if (!UsedRegs.empty() || II.getImplicitDefs()) in EmitMachineNode()
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| D | ScheduleDAGFast.cpp | 443 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT()
522 for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) { in DelayForLiveRegsBottomUp()
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| D | ScheduleDAGRRList.cpp | 1199 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT()
1328 for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) in DelayForLiveRegsBottomUp()
2698 = TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs(); in canClobberReachingPhysRegUse()
2734 const MCPhysReg *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs(); in canClobberPhysRegDefs()
2741 TII->get(SUNode->getMachineOpcode()).getImplicitDefs(); in canClobberPhysRegDefs()
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| D | ScheduleDAGSDNodes.cpp | 446 TII->get(N->getMachineOpcode()).getImplicitDefs()) { in AddSchedEdges()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 437 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT()
515 for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) { in DelayForLiveRegsBottomUp()
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| D | InstrEmitter.cpp | 827 bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr; in EmitMachineNode()
918 unsigned Reg = II.getImplicitDefs()[i - NumDefs]; in EmitMachineNode()
953 if (!UsedRegs.empty() || II.getImplicitDefs()) in EmitMachineNode()
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| D | ScheduleDAGRRList.cpp | 1275 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT()
1415 for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) in DelayForLiveRegsBottomUp()
2825 = TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs(); in canClobberReachingPhysRegUse()
2861 const MCPhysReg *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs(); in canClobberPhysRegDefs()
2868 TII->get(SUNode->getMachineOpcode()).getImplicitDefs(); in canClobberPhysRegDefs()
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| D | ScheduleDAGSDNodes.cpp | 447 TII->get(N->getMachineOpcode()).getImplicitDefs()) { in AddSchedEdges()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/ |
| D | MCInstrDescView.cpp | 38 for (const llvm::MCPhysReg *MCPhysReg = MCInstrDesc.getImplicitDefs(); in Instruction()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/ |
| D | InstrBuilder.cpp | 227 Write.RegisterID = MCDesc.getImplicitDefs()[CurrentDef]; in populateWrites()
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.cpp | 87 if (const MCPhysReg *ImpDef = MCID.getImplicitDefs()) in init()
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| /external/llvm/lib/Target/Hexagon/ |
| D | RDFGraph.cpp | 703 if (!D.getImplicitDefs() && !D.getImplicitUses()) in isFixedReg()
712 const MCPhysReg *ImpR = Op.isDef() ? D.getImplicitDefs() in isFixedReg()
1194 if (const uint16_t *ImpD = In.getDesc().getImplicitDefs()) in buildStmt()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.cpp | 101 if (const MCPhysReg *ImpDef = MCID.getImplicitDefs()) in init()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | RDFGraph.cpp | 647 if (!D.getImplicitDefs() && !D.getImplicitUses()) in isFixedReg()
656 const MCPhysReg *ImpR = Op.isDef() ? D.getImplicitDefs() in isFixedReg()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 229 for (const MCPhysReg *Regs = MCID.getImplicitDefs(); *Regs; ++Regs) in HasImplicitCPSRDef()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 432 const MCPhysReg Reg = Desc.getImplicitDefs()[I]; in clearsSuperRegisters()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | RegAllocFast.cpp | 1061 if (const unsigned *Defs = (*I)->getImplicitDefs()) in runOnMachineFunction()
|