| /external/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBank.cpp | 26 assert(ContainedRegClasses.size() == TRI.getNumRegClasses() && in verify()
28 for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) { in verify()
92 assert(ContainedRegClasses.size() == TRI->getNumRegClasses() && in print()
96 for (unsigned RCId = 0, End = TRI->getNumRegClasses(); RCId != End; ++RCId) { in print()
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| D | RegisterBankInfo.cpp | 71 unsigned NbOfRegClasses = TRI.getNumRegClasses(); in addRegBankCoverage()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBank.cpp | 33 for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) { in verify()
99 assert(ContainedRegClasses.size() == TRI->getNumRegClasses() && in print()
103 for (unsigned RCId = 0, End = TRI->getNumRegClasses(); RCId != End; ++RCId) { in print()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 672 return RCInfos[getNumRegClasses() * HwMode + RC.getID()]; in getRegClassInfo()
683 unsigned getNumRegClasses() const { in getNumRegClasses() function
690 assert(i < getNumRegClasses() && "Register Class ID out of range"); in getRegClass()
1034 : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
1133 : NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) { in BitMaskClassIterator()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 643 unsigned getNumRegClasses() const { in getNumRegClasses() function
650 assert(i < getNumRegClasses() && "Register Class ID out of range"); in getRegClass()
964 : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
1065 : NumRegClasses(TRI.getNumRegClasses()), Base(0), Idx(0), ID(0), in BitMaskClassIterator()
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| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCRegisterInfo.h | 293 unsigned getNumRegClasses() const { in getNumRegClasses() function
300 assert(i < getNumRegClasses() && "Register Class ID out of range"); in getRegClass()
|
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 451 unsigned getNumRegClasses() const { in getNumRegClasses() function
458 assert(i < getNumRegClasses() && "Register Class ID out of range"); in getRegClass()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 37 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
|
| D | MachineLICM.cpp | 326 unsigned NumRC = TRI->getNumRegClasses(); in runOnMachineFunction()
|
| /external/swiftshader/third_party/LLVM/lib/Target/ |
| D | TargetRegisterInfo.cpp | 116 for (unsigned Base = 0, BaseE = getNumRegClasses(); Base < BaseE; Base += 32) in getCommonSubClass()
|
| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 411 unsigned getNumRegClasses() const { in getNumRegClasses() function
418 assert(i < getNumRegClasses() && "Register Class ID out of range"); in getRegClass()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 433 unsigned getNumRegClasses() const { in getNumRegClasses() function
440 assert(i < getNumRegClasses() && "Register Class ID out of range"); in getRegClass()
|
| /external/llvm/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 42 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
|
| D | TargetRegisterInfo.cpp | 184 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32) in firstCommonClass()
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| D | TargetLoweringBase.cpp | 1270 BitVector SuperRegRC(TRI->getNumRegClasses()); in findRepresentativeClass()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 51 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
|
| D | TargetRegisterInfo.cpp | 245 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32) in firstCommonClass()
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| D | TargetLoweringBase.cpp | 1040 BitVector SuperRegRC(TRI->getNumRegClasses()); in findRepresentativeClass()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 55 unsigned NumRC = TRI->getNumRegClasses(); in ResourcePriorityQueue()
|
| D | ScheduleDAGRRList.cpp | 1745 unsigned NumRC = TRI->getNumRegClasses(); in RegReductionPQBase()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 55 unsigned NumRC = TRI->getNumRegClasses(); in ResourcePriorityQueue()
|
| /external/llvm/lib/CodeGen/MIRParser/ |
| D | MIRParser.cpp | 720 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; ++I) { in initNames2RegClasses()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/MIRParser/ |
| D | MIRParser.cpp | 849 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; ++I) { in initNames2RegClasses()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXAsmPrinter.cpp | 1675 for (unsigned i=0; i< TRI->getNumRegClasses(); i++) { in setAndEmitFunctionVirtualRegisters()
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXAsmPrinter.cpp | 1690 for (unsigned i=0; i< TRI->getNumRegClasses(); i++) { in setAndEmitFunctionVirtualRegisters()
|