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Searched refs:getReg (Results 1 – 25 of 1046) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/X86/InstPrinter/
DX86InstComments.cpp37 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
38 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
43 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
44 Src1Name = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
49 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
50 Src1Name = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
55 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
58 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
64 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
67 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp218 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts()
241 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg()); in printMasking()
271 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMA3Comments()
276 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); in printFMA3Comments()
277 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMA3Comments()
282 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMA3Comments()
287 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); in printFMA3Comments()
288 Mul2Name = getRegName(MI->getOperand(1).getReg()); in printFMA3Comments()
293 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMA3Comments()
298 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); in printFMA3Comments()
[all …]
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp176 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandVectorVT()
281 MaskRegName = getRegName(MI->getOperand(1).getReg()); in getMaskName()
345 MaskRegName = getRegName(MI->getOperand(2).getReg()); in getMaskName()
384 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
393 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
394 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
400 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
409 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
410 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
416 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZAsmPrinter.cpp34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
61 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
62 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
63 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
87 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorLoad()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZAsmPrinter.cpp34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
61 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
62 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
63 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
87 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorLoad()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/
DLegalizationArtifactCombiner.h40 MI.getOperand(1).getReg(), MRI)) { in tryCombineAnyExt()
42 unsigned DstReg = MI.getOperand(0).getReg(); in tryCombineAnyExt()
43 unsigned SrcReg = DefMI->getOperand(1).getReg(); in tryCombineAnyExt()
59 MI.getOperand(1).getReg(), MRI)) { in tryCombineZExt()
60 unsigned DstReg = MI.getOperand(0).getReg(); in tryCombineZExt()
67 unsigned ZExtSrc = MI.getOperand(1).getReg(); in tryCombineZExt()
71 unsigned TruncSrc = DefMI->getOperand(1).getReg(); in tryCombineZExt()
87 MI.getOperand(1).getReg(), MRI)) { in tryCombineSExt()
88 unsigned DstReg = MI.getOperand(0).getReg(); in tryCombineSExt()
96 unsigned SExtSrc = MI.getOperand(1).getReg(); in tryCombineSExt()
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmWriter.inc12884 MI->getOperand(0).getReg() == AArch64::WZR &&
12886 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg())) {
12894 MI->getOperand(0).getReg() == AArch64::WZR &&
12896 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
12898 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
12906 MI->getOperand(0).getReg() == AArch64::WZR &&
12908 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
12910 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
12917 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
12919 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
[all …]
DAArch64GenAsmWriter1.inc13572 MI->getOperand(0).getReg() == AArch64::WZR &&
13574 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg())) {
13582 MI->getOperand(0).getReg() == AArch64::WZR &&
13584 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
13586 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
13594 MI->getOperand(0).getReg() == AArch64::WZR &&
13596 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
13598 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
13605 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
13607 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCVSXCopy.cpp101 if ( IsVSReg(DstMO.getReg(), MRI) && in processBlock()
102 !IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
107 IsVRReg(SrcMO.getReg(), MRI) ? &PPC::VSHRCRegClass : in processBlock()
109 assert((IsF8Reg(SrcMO.getReg(), MRI) || in processBlock()
110 IsVRReg(SrcMO.getReg(), MRI) || in processBlock()
111 IsVSSReg(SrcMO.getReg(), MRI) || in processBlock()
112 IsVSFReg(SrcMO.getReg(), MRI)) && in processBlock()
121 .addImm(IsVRReg(SrcMO.getReg(), MRI) ? PPC::sub_128 : in processBlock()
126 } else if (!IsVSReg(DstMO.getReg(), MRI) && in processBlock()
127 IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp138 Args.push_back({MI.getOperand(i).getReg(), OpType}); in simpleLibcall()
139 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType}, in simpleLibcall()
169 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType}, in conversionLibcall()
170 {{MI.getOperand(1).getReg(), FromType}}); in conversionLibcall()
175 LLT LLTy = MRI.getType(MI.getOperand(0).getReg()); in libcall()
209 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); in libcall()
210 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); in libcall()
221 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); in libcall()
222 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); in libcall()
234 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); in libcall()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/unittests/CodeGen/GlobalISel/
DPatternMatchTest.cpp119 Copies.push_back(MI.getOperand(0).getReg()); in collectCopies()
139 bool match = mi_match(MIBCst->getOperand(0).getReg(), MRI, m_ICst(Cst)); in TEST()
162 mi_match(MIBAdd->getOperand(0).getReg(), MRI, m_GAdd(m_Reg(), m_Reg())); in TEST()
165 match = mi_match(MIBAdd->getOperand(0).getReg(), MRI, in TEST()
175 match = mi_match(MIBMul->getOperand(0).getReg(), MRI, in TEST()
178 ASSERT_EQ(Src0, MIBAdd->getOperand(0).getReg()); in TEST()
182 match = mi_match(MIBMul->getOperand(0).getReg(), MRI, in TEST()
194 match = mi_match(MIBMul2->getOperand(0).getReg(), MRI, in TEST()
202 match = mi_match(MIBSub->getOperand(0).getReg(), MRI, in TEST()
209 match = mi_match(MIBFMul->getOperand(0).getReg(), MRI, in TEST()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp98 printRegName(O, Dst.getReg()); in printInst()
100 printRegName(O, MO1.getReg()); in printInst()
103 printRegName(O, MO2.getReg()); in printInst()
120 printRegName(O, Dst.getReg()); in printInst()
122 printRegName(O, MO1.getReg()); in printInst()
138 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
152 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
157 printRegName(O, MI->getOperand(1).getReg()); in printInst()
167 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
181 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp69 O << '\t' << getRegisterName(Dst.getReg()) in printInst()
70 << ", " << getRegisterName(MO1.getReg()); in printInst()
72 O << ", " << getRegisterName(MO2.getReg()); in printInst()
88 O << '\t' << getRegisterName(Dst.getReg()) in printInst()
89 << ", " << getRegisterName(MO1.getReg()); in printInst()
104 MI->getOperand(0).getReg() == ARM::SP) { in printInst()
114 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP && in printInst()
118 O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}"; in printInst()
125 MI->getOperand(0).getReg() == ARM::SP) { in printInst()
135 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP && in printInst()
[all …]
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp90 printRegName(O, Dst.getReg()); in printInst()
92 printRegName(O, MO1.getReg()); in printInst()
95 printRegName(O, MO2.getReg()); in printInst()
112 printRegName(O, Dst.getReg()); in printInst()
114 printRegName(O, MO1.getReg()); in printInst()
130 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
144 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
149 printRegName(O, MI->getOperand(1).getReg()); in printInst()
159 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
173 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
[all …]
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp189 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
190 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
207 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
208 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
228 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
229 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
238 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
239 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
248 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
249 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp197 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
198 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
215 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
216 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
236 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
237 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
246 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
247 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
256 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
257 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPURegisterBankInfo.cpp58 const MachineInstr *Def = MRI.getVRegDef(MO.getReg()); in isConstant()
109 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); in getInstrAlternativeMappings()
138 unsigned Size = getSizeInBits(MI.getOperand(2).getReg(), MRI, *TRI); in getInstrAlternativeMappings()
196 unsigned Reg = MI.getOperand(i).getReg(); in isSALUMapping()
211 unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI); in getDefaultMappingSOP()
225 unsigned Size0 = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); in getDefaultMappingVOP()
231 unsigned Reg1 = MI.getOperand(OpdIdx).getReg(); in getDefaultMappingVOP()
237 unsigned Size = getSizeInBits(MI.getOperand(OpdIdx).getReg(), MRI, *TRI); in getDefaultMappingVOP()
251 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); in getInstrMappingForLoad()
252 unsigned PtrSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI); in getInstrMappingForLoad()
[all …]
DSIShrinkInstructions.cpp87 if (!Src1->isReg() || !TRI.isVGPR(MRI, Src1->getReg())) in canShrink()
95 if (!Src2->isReg() || !TRI.isVGPR(MRI, Src2->getReg()) || in canShrink()
106 if (Src1 && (!Src1->isReg() || !TRI.isVGPR(MRI, Src1->getReg()) || in canShrink()
132 unsigned Reg = Src0.getReg(); in foldImmediates()
181 if (Use.isUse() && Use.getReg() == AMDGPU::VCC) { in copyFlagsToImplicitVCC()
312 TargetRegisterInfo::isPhysicalRegister(MI.getOperand(0).getReg())) { in runOnMachineFunction()
368 if (TargetRegisterInfo::isVirtualRegister(Dest->getReg()) && in runOnMachineFunction()
370 MRI.setRegAllocationHint(Dest->getReg(), 0, Src0->getReg()); in runOnMachineFunction()
371 MRI.setRegAllocationHint(Src0->getReg(), 0, Dest->getReg()); in runOnMachineFunction()
375 if (Src0->isReg() && Src0->getReg() == Dest->getReg()) { in runOnMachineFunction()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCMIPeephole.cpp132 unsigned Reg = Op->getReg(); in getVRegDefOrNull()
300 TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI); in simplifyCode()
302 TRI->lookThruCopyLike(MI.getOperand(2).getReg(), MRI); in simplifyCode()
317 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI); in simplifyCode()
331 MI.getOperand(0).getReg()) in simplifyCode()
343 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI); in simplifyCode()
345 TRI->lookThruCopyLike(DefMI->getOperand(2).getReg(), MRI); in simplifyCode()
352 MI.getOperand(0).getReg()) in simplifyCode()
365 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg()); in simplifyCode()
366 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg()); in simplifyCode()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMRegisterBankInfo.cpp250 LLT LargeTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
260 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
273 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
280 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
294 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
295 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
303 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
304 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
313 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
314 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DMachineCopyPropagation.cpp199 unsigned PreviousSrc = PreviousCopy.getOperand(1).getReg(); in isNopCopy()
200 unsigned PreviousDef = PreviousCopy.getOperand(0).getReg(); in isNopCopy()
238 unsigned CopyDef = Copy.getOperand(0).getReg(); in eraseIfRedundant()
257 unsigned CopySrcReg = Copy.getOperand(1).getReg(); in isForwardableRegClassCopy()
285 TRI->getMinimalPhysRegClass(UseI.getOperand(0).getReg()); in isForwardableRegClassCopy()
308 MIUse.isUse() && TRI->regsOverlap(Use.getReg(), MIUse.getReg())) in hasImplicitOverlap()
335 if (!MOUse.getReg()) in forwardUses()
344 auto CI = AvailCopyMap.find(MOUse.getReg()); in forwardUses()
349 unsigned CopyDstReg = Copy.getOperand(0).getReg(); in forwardUses()
351 unsigned CopySrcReg = CopySrc.getReg(); in forwardUses()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp214 unsigned R = Op.getReg(); in isFixedInstr()
262 unsigned T = MO.getReg(); in partitionRegisters()
376 unsigned Rs = MI->getOperand(1).getReg(); in profit()
377 unsigned Rt = MI->getOperand(2).getReg(); in profit()
444 if (Op.isReg() && Part.count(Op.getReg())) in isProfitable()
503 unsigned PR = Cond[1].getReg(); in collectIndRegsForLoop()
511 CmpI = MRI->getVRegDef(CmpI->getOperand(1).getReg()); in collectIndRegsForLoop()
539 unsigned R = MD.getReg(); in collectIndRegsForLoop()
555 unsigned T = UseI->getOperand(0).getReg(); in collectIndRegsForLoop()
607 unsigned R = Op.getReg(); in createHalfInstr()
[all …]
/external/capstone/arch/Mips/
DMipsDisassembler.c460 static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo) in getReg() function
551 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); in DecodeAddiGroupBranch_4()
553 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); in DecodeAddiGroupBranch_4()
587 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); in DecodeDaddiGroupBranch_4()
589 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); in DecodeDaddiGroupBranch_4()
626 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); in DecodeBlezlGroupBranch_4()
628 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); in DecodeBlezlGroupBranch_4()
667 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); in DecodeBgtzlGroupBranch_4()
669 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); in DecodeBgtzlGroupBranch_4()
711 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); in DecodeBgtzGroupBranch_4()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp578 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { in getReg() function
636 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
638 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
650 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
688 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
691 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
708 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
710 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
715 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp190 unsigned R = Op.getReg(); in isFixedInstr()
239 unsigned T = MO.getReg(); in partitionRegisters()
397 if (Op.isReg() && Part.count(Op.getReg())) in isProfitable()
456 unsigned PR = Cond[1].getReg(); in collectIndRegsForLoop()
464 CmpI = MRI->getVRegDef(CmpI->getOperand(1).getReg()); in collectIndRegsForLoop()
491 unsigned R = MD.getReg(); in collectIndRegsForLoop()
507 unsigned T = UseI->getOperand(0).getReg(); in collectIndRegsForLoop()
560 unsigned R = Op.getReg(); in createHalfInstr()
601 UUPairMap::const_iterator F = PairMap.find(ValOp.getReg()); in splitMemRef()
608 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
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