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Searched refs:getRegInfo (Results 1 – 25 of 597) sorted by relevance

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/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp123 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2); in getCalleeSavedRegs()
383 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerDynamicAlloc()
407 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in lowerDynamicAlloc()
415 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in lowerDynamicAlloc()
432 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in lowerDynamicAlloc()
440 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in lowerDynamicAlloc()
504 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
516 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
549 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
561 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp160 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2); in getCalleeSavedRegs()
457 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerDynamicAlloc()
486 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in lowerDynamicAlloc()
494 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in lowerDynamicAlloc()
511 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in lowerDynamicAlloc()
519 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in lowerDynamicAlloc()
585 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
597 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
630 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
642 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
[all …]
/external/llvm/lib/Target/AMDGPU/
DSIFrameLowering.cpp65 MachineRegisterInfo &MRI = MF.getRegInfo(); in emitPrologue()
156 MachineRegisterInfo &MRI = MF.getRegInfo(); in emitPrologue()
175 MachineRegisterInfo &MRI = MF.getRegInfo(); in emitPrologue()
314 MF.getRegInfo().addLiveIn(WorkGroupIDSGPR); in emitDebuggerPrologue()
320 MF.getRegInfo().createVirtualRegister(&AMDGPU::VGPR_32RegClass); in emitDebuggerPrologue()
331 MF.getRegInfo().addLiveIn(WorkItemIDVGPR); in emitDebuggerPrologue()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/
DNVPTXPeephole.cpp83 const auto &MRI = MF.getRegInfo(); in isCVTAToLocalCombinationCandidate()
108 const auto &MRI = MF.getRegInfo(); in CombineCVTAToLocal()
147 const auto &MRI = MF.getRegInfo(); in runOnMachineFunction()
/external/llvm/lib/Target/NVPTX/
DNVPTXPeephole.cpp83 const auto &MRI = MF.getRegInfo(); in isCVTAToLocalCombinationCandidate()
108 const auto &MRI = MF.getRegInfo(); in CombineCVTAToLocal()
147 const auto &MRI = MF.getRegInfo(); in runOnMachineFunction()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMFrameLowering.cpp374 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) && in emitEpilogue()
576 MF.getRegInfo().isLiveIn(Reg)) in emitPushInst()
883 MF.getRegInfo().setPhysRegUsed(ARM::R4); in processFunctionBeforeCalleeSavedScan()
888 MF.getRegInfo().setPhysRegUsed(ARM::LR); in processFunctionBeforeCalleeSavedScan()
898 MF.getRegInfo().setPhysRegUsed(ARM::R4); in processFunctionBeforeCalleeSavedScan()
903 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister()); in processFunctionBeforeCalleeSavedScan()
911 if (MF.getRegInfo().isPhysRegUsed(Reg)) { in processFunctionBeforeCalleeSavedScan()
918 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) { in processFunctionBeforeCalleeSavedScan()
1009 MF.getRegInfo().setPhysRegUsed(ARM::LR); in processFunctionBeforeCalleeSavedScan()
1018 MF.getRegInfo().setPhysRegUsed(FramePtr); in processFunctionBeforeCalleeSavedScan()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPUInstructionSelector.cpp67 MachineRegisterInfo &MRI = MF->getRegInfo(); in selectCOPY()
89 MachineRegisterInfo &MRI = MF->getRegInfo(); in getSubOperand64()
125 MachineRegisterInfo &MRI = MF->getRegInfo(); in selectG_ADD()
172 MachineRegisterInfo &MRI = MF->getRegInfo(); in selectG_IMPLICIT_DEF()
196 MachineRegisterInfo &MRI = MF->getRegInfo(); in selectG_INTRINSIC()
240 MachineRegisterInfo &MRI = MF->getRegInfo(); in selectG_INTRINSIC_W_SIDE_EFFECTS()
283 MachineRegisterInfo &MRI = MF->getRegInfo(); in selectG_STORE()
325 MachineRegisterInfo &MRI = MF->getRegInfo(); in selectG_CONSTANT()
522 MachineRegisterInfo &MRI = MF->getRegInfo(); in selectSMRD()
581 MachineRegisterInfo &MRI = MF->getRegInfo(); in selectG_LOAD()
DSIFrameLowering.cpp63 MachineRegisterInfo &MRI = MF.getRegInfo(); in emitFlatScratchInit()
106 MachineRegisterInfo &MRI = MF.getRegInfo(); in getReservedPrivateSegmentBufferReg()
157 MachineRegisterInfo &MRI = MF.getRegInfo(); in getReservedPrivateSegmentWaveByteOffsetReg()
239 MachineRegisterInfo &MRI = MF.getRegInfo(); in emitEntryFunctionPrologue()
407 MF.getRegInfo().addLiveIn(GitPtrLo); in emitEntryFunctionScratchSetup()
521 MachineRegisterInfo &MRI = MF->getRegInfo(); in findScratchNonCalleeSaveRegister()
794 MF.getRegInfo().addLiveIn(WorkGroupIDSGPR); in emitDebuggerPrologue()
800 MF.getRegInfo().createVirtualRegister(&AMDGPU::VGPR_32RegClass); in emitDebuggerPrologue()
811 MF.getRegInfo().addLiveIn(WorkItemIDVGPR); in emitDebuggerPrologue()
DAMDGPURegisterBankInfo.cpp57 const MachineRegisterInfo &MRI = MF->getRegInfo(); in isConstant()
103 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getInstrAlternativeMappings()
194 const MachineRegisterInfo &MRI = MF.getRegInfo(); in isSALUMapping()
207 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getDefaultMappingSOP()
221 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getDefaultMappingVOP()
249 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getInstrMappingForLoad()
301 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getInstrMapping()
DGCNHazardRecognizer.cpp413 if (!Use.isReg() || TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in checkVMEMHazards()
434 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkDPPHazards()
565 const MachineRegisterInfo &MRI = MF.getRegInfo(); in checkVALUHazards()
587 const MachineRegisterInfo &MRI = MF.getRegInfo(); in checkInlineAsmHazards()
604 const MachineRegisterInfo &MRI = MF.getRegInfo(); in checkRWLaneHazards()
651 if (!Use.isReg() || TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkAnyInstHazards()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DAllocationOrder.cpp29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg); in AllocationOrder()
31 VRM.getRegInfo().getRegAllocationHint(VirtReg); in AllocationOrder()
DVirtRegMap.cpp56 MRI = &mf.getRegInfo(); in runOnMachineFunction()
79 ImplicitDefed.resize(MF->getRegInfo().getNumVirtRegs()); in runOnMachineFunction()
93 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs(); in grow()
133 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg); in assignVirt2StackSlot()
357 const MachineRegisterInfo &MRI = MF->getRegInfo(); in print()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
DWebAssemblyRegNumbering.cpp68 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnMachineFunction()
88 unsigned NumVRegs = MF.getRegInfo().getNumVirtRegs(); in runOnMachineFunction()
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaISelLowering.cpp42 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); in AddLiveIn()
43 MF.getRegInfo().addLiveIn(PReg, VReg); in AddLiveIn()
503 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) in LowerReturn()
504 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg); in LowerReturn()
520 if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(), in LowerReturn()
521 DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg1) in LowerReturn()
522 == DAG.getMachineFunction().getRegInfo().liveout_end()) in LowerReturn()
523 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg1); in LowerReturn()
526 if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(), in LowerReturn()
527 DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg2) in LowerReturn()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DLivePhysRegs.cpp179 const MachineRegisterInfo &MRI = MF.getRegInfo(); in addCalleeSavedRegs()
250 const MachineRegisterInfo &MRI = MF.getRegInfo(); in computeLiveIns()
261 const MachineRegisterInfo &MRI = MF.getRegInfo(); in addLiveIns()
282 const MachineRegisterInfo &MRI = MF.getRegInfo(); in recomputeLivenessFlags()
DTargetFrameLoweringImpl.cpp85 const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs(); in determineCalleeSaves()
110 const MachineRegisterInfo &MRI = MF.getRegInfo(); in determineCalleeSaves()
DMIRCanonicalizerPass.cpp241 MachineRegisterInfo *MRI = &MBB->getParent()->getRegInfo(); in rescheduleCanonically()
323 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); in propagateLocalCopies()
368 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); in populateCandidates()
402 const MachineRegisterInfo &MRI = MF.getRegInfo(); in doCandidateWalk()
663 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnBasicBlock()
797 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnMachineFunction()
DRegAllocPBQP.cpp459 if (!MF.getRegInfo().isAllocatable(DstReg)) in apply()
558 const MachineRegisterInfo &MRI = MF.getRegInfo(); in findVRegIntervalsToAlloc()
571 const MCPhysReg *CSR = MF.getRegInfo().getCalleeSavedRegs(); in isACalleeSavedRegister()
583 const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo(); in initializeGraph()
746 MachineRegisterInfo &MRI = MF.getRegInfo(); in finalizeAlloc()
760 if (!VRM.getRegInfo().isReserved(CandidateReg)) { in finalizeAlloc()
802 MF.getRegInfo().freezeReservedRegs(MF); in runOnMachineFunction()
880 const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo(); in PrintNodeInfo()
DVirtRegMap.cpp64 MRI = &mf.getRegInfo(); in runOnMachineFunction()
78 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs(); in grow()
90 assert(!getRegInfo().isReserved(physReg) && in assignVirt2Phys()
125 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg); in assignVirt2StackSlot()
241 MRI = &MF->getRegInfo(); in runOnMachineFunction()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyRegNumbering.cpp63 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnMachineFunction()
90 unsigned NumVRegs = MF.getRegInfo().getNumVirtRegs(); in runOnMachineFunction()
DWebAssemblyFrameLowering.cpp87 MachineRegisterInfo &MRI = MF.getRegInfo(); in writeSPToMemory()
133 auto &MRI = MF.getRegInfo(); in emitPrologue()
186 auto &MRI = MF.getRegInfo(); in emitEpilogue()
DWebAssemblyRegisterInfo.cpp62 MachineRegisterInfo &MRI = MF.getRegInfo(); in eliminateFrameIndex()
88 MachineInstr *Def = MF.getRegInfo().getUniqueVRegDef(OtherMOReg); in eliminateFrameIndex()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86RegisterBankInfo.cpp146 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getSameOperandsMapping()
162 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getInstrMapping()
255 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getInstrAlternativeMappings()
/external/llvm/lib/CodeGen/
DVirtRegMap.cpp55 MRI = &mf.getRegInfo(); in runOnMachineFunction()
69 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs(); in grow()
104 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg); in assignVirt2StackSlot()
216 MRI = &MF->getRegInfo(); in runOnMachineFunction()
/external/swiftshader/third_party/llvm-7.0/llvm/unittests/CodeGen/GlobalISel/
DPatternMatchTest.cpp135 MachineRegisterInfo &MRI = MF->getRegInfo(); in TEST()
156 MachineRegisterInfo &MRI = MF->getRegInfo(); in TEST()
283 MachineRegisterInfo &MRI = MF->getRegInfo(); in TEST()
354 MachineRegisterInfo &MRI = MF->getRegInfo(); in TEST()
410 MachineRegisterInfo &MRI = MF->getRegInfo(); in TEST()
457 MachineRegisterInfo &MRI = MF->getRegInfo(); in TEST()

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