| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/ |
| D | XCoreMachineFunctionInfo.cpp | 44 LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true); in createLRSpillSlot()
46 LRSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), in createLRSpillSlot()
60 FPSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), in createFPSpillSlot()
73 unsigned Size = TRI.getSpillSize(RC); in createEHSpillSlot()
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| D | XCoreFrameLowering.cpp | 585 unsigned Size = TRI.getSpillSize(RC); in processFunctionBeforeFrameFinalized()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsMachineFunction.cpp | 63 EhDataRegFI[I] = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC), in createEhDataRegsFI()
78 TRI.getSpillSize(RC), TRI.getSpillAlignment(RC), false); in createISRRegFI()
101 TRI.getSpillSize(*RC), TRI.getSpillAlignment(*RC), false); in getMoveF64ViaSpillFI()
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| D | MipsFrameLowering.cpp | 128 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R)); in estimateStackSize()
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| D | MipsSEFrameLowering.cpp | 895 int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC), in determineCalleeSaves()
912 int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC), in determineCalleeSaves()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
| D | ARCInstrInfo.cpp | 297 assert(TRI->getSpillSize(*RC) == 4 && in storeRegToStackSlot()
324 assert(TRI->getSpillSize(*RC) == 4 && in loadRegFromStackSlot()
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| D | ARCFrameLowering.cpp | 423 RegInfo->getSpillSize(*RC), RegInfo->getSpillAlignment(*RC), false); in processFunctionBeforeFrameFinalized()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonVExtract.cpp | 126 int FI = MFI.CreateSpillStackObject(HRI.getSpillSize(VecRC), in runOnMachineFunction()
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| D | HexagonFrameLowering.cpp | 1487 int FI = MFI.CreateFixedSpillStackObject(TRI->getSpillSize(*RC), S->Offset); in assignCalleeSavedSpillSlots()
1499 unsigned Size = TRI->getSpillSize(*RC); in assignCalleeSavedSpillSlots()
1724 unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass); in expandStoreVec2()
1771 unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass); in expandLoadVec2()
1935 unsigned S = HRI.getSpillSize(*RC), A = HRI.getSpillAlignment(*RC); in determineCalleeSaves()
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| D | HexagonInstrInfo.cpp | 1087 unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1110 unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
2644 unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass); in isValidOffset()
4159 return HRI.getSpillSize(Hexagon::HvxVRRegClass); in getMemAccessSize()
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| D | HexagonPatternsHVX.td | 71 int32_t VecSize = HRI->getSpillSize(Hexagon::HvxVRRegClass);
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | StackMaps.cpp | 164 Locs.emplace_back(Location::Register, TRI->getSpillSize(*RC), in parseOperand()
250 unsigned Size = TRI->getSpillSize(*TRI->getMinimalPhysRegClass(Reg)); in createLiveOutReg()
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| D | TargetInstrInfo.cpp | 386 Size = TRI->getSpillSize(*RC); in getStackSlotRange()
403 assert(TRI->getSpillSize(*RC) >= (Offset + Size) && "bad subregister range"); in getStackSlotRange()
406 Offset = TRI->getSpillSize(*RC) - (Offset + Size); in getStackSlotRange()
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| D | VirtRegMap.cpp | 96 unsigned Size = TRI->getSpillSize(*RC); in createSpillSlot()
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| D | RegisterScavenging.cpp | 468 unsigned NeedSize = TRI->getSpillSize(RC); in spill()
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| D | TargetLoweringBase.cpp | 1049 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC)) in findRepresentativeClass()
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| D | RegAllocFast.cpp | 240 unsigned Size = TRI->getSpillSize(RC); in getStackSpaceFor()
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| D | PrologEpilogInserter.cpp | 376 unsigned Size = RegInfo->getSpillSize(*RC); in assignCalleeSavedSpillSlots()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVFrameLowering.cpp | 260 RegInfo->getSpillSize(*RC), RegInfo->getSpillAlignment(*RC), false); in processFunctionBeforeFrameFinalized()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 320 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize() function
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIFrameLowering.cpp | 731 TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false); in processFunctionBeforeFrameFinalized()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 3135 switch (STI.getRegisterInfo()->getSpillSize(*RC)) { in getLoadStoreRegOpcode()
3299 assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) && in storeRegToStackSlot()
3301 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16); in storeRegToStackSlot()
3319 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16); in storeRegToAddr()
3339 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16); in loadRegFromStackSlot()
3355 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16); in loadRegFromAddr()
5525 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16); in unfoldMemoryOperand()
5594 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16); in unfoldMemoryOperand()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 1508 unsigned Size = TRI->getSpillSize(RC); in determineCalleeSaves()
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| D | AArch64InstrInfo.cpp | 2749 switch (TRI->getSpillSize(*RC)) { in storeRegToStackSlot()
2857 switch (TRI->getSpillSize(*RC)) { in loadRegFromStackSlot()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 1935 unsigned Size = TRI.getSpillSize(RC); in addScavengingSpillSlot()
|