| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| D | X86GenFastISel.inc | 117 if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) {
132 if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) {
144 if ((Subtarget->hasAVX512())) {
153 if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) {
162 if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) {
171 if ((Subtarget->hasAVX512())) {
215 if ((Subtarget->hasAVX512())) {
221 if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) {
228 if ((Subtarget->hasAVX512())) {
234 if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) {
[all …]
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| D | X86GenCallingConv.inc | 941 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
1588 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
1721 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
2021 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
2453 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
3151 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
3727 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
3927 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 135 if (!Subtarget.hasAVX512() && in getLargestLegalSuperClass()
156 if (Subtarget.hasAVX512() && in getLargestLegalSuperClass()
272 bool HasAVX512 = Subtarget.hasAVX512(); in getCalleeSavedRegs()
395 bool HasAVX512 = Subtarget.hasAVX512(); in getCallPreservedMask()
570 if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) { in getReservedRegs()
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| D | X86Subtarget.h | 546 bool hasAVX512() const { return X86SSELevel >= AVX512F; } in hasAVX512() function
663 return hasAVX512() && (!hasVLX() || getPreferVectorWidth() >= 512); in canExtendTo512DQ()
672 return hasAVX512() && (canExtendTo512DQ() || RequiredVectorWidth > 256); in useAVX512Regs()
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| D | X86Subtarget.cpp | 282 if (hasAVX512() || (hasAVX2() && hasFastGather())) in initSubtargetFeatures()
284 if (hasAVX512()) in initSubtargetFeatures()
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| D | X86LegalizerInfo.cpp | 395 if (!Subtarget.hasAVX512()) in setLegalizerInfoAVX512()
441 if (!(Subtarget.hasAVX512() && Subtarget.hasDQI())) in setLegalizerInfoAVX512DQ()
460 if (!(Subtarget.hasAVX512() && Subtarget.hasBWI())) in setLegalizerInfoAVX512BW()
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| D | X86TargetTransformInfo.cpp | 125 if (Vector && ST->hasAVX512()) in getNumberOfRegisters()
135 if (ST->hasAVX512() && PreferVectorWidth >= 512) in getRegisterBitWidth()
319 ST->hasAVX512()) { in getArithmeticInstrCost()
499 if (ST->hasAVX512()) in getArithmeticInstrCost()
938 if (ST->hasAVX512()) in getShuffleCost()
1474 if (ST->hasAVX512()) in getCastInstrCost()
1567 if (ST->hasAVX512()) in getCmpSelInstrCost()
1829 if (ST->hasAVX512()) in getIntrinsicInstrCost()
1995 if (!ST->hasAVX512()) in getMaskedMemoryOpCost()
2208 if (ST->hasAVX512()) in getMinMaxReductionCost()
[all …]
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| D | X86InstructionSelector.cpp | 182 return STI.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass; in getRegClass()
184 return STI.hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass; in getRegClass()
186 return STI.hasAVX512() ? &X86::VR128XRegClass : &X86::VR128RegClass; in getRegClass()
188 return STI.hasAVX512() ? &X86::VR256XRegClass : &X86::VR256RegClass; in getRegClass()
397 bool HasAVX512 = STI.hasAVX512(); in getLoadStoreOp()
1059 bool HasAVX512 = STI.hasAVX512(); in selectExtract()
1192 bool HasAVX512 = STI.hasAVX512(); in selectInsert()
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| D | X86FastISel.cpp | 326 bool HasAVX512 = Subtarget->hasAVX512(); in X86FastEmitLoad()
503 bool HasAVX512 = Subtarget->hasAVX512(); in X86FastEmitStore()
1351 bool HasAVX512 = Subtarget->hasAVX512(); in X86ChooseCmpOpcode()
2231 if (Subtarget->hasAVX512()) { in X86FastEmitSSESelect()
2425 bool HasAVX512 = Subtarget->hasAVX512(); in X86SelectIntToFP()
2517 bool HasAVX512 = Subtarget->hasAVX512(); in X86SelectFPExt()
2532 bool HasAVX512 = Subtarget->hasAVX512(); in X86SelectFPTrunc()
2836 unsigned AVXLevel = Subtarget->hasAVX512() ? 2 : in fastLowerIntrinsicCall()
3039 unsigned AVXLevel = Subtarget->hasAVX512() ? 2 : in fastLowerIntrinsicCall()
3686 !(Subtarget->hasAVX512() && SVT.is512BitVector() && in fastSelectInstruction()
[all …]
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| D | X86EvexToVex.cpp | 101 if (!ST.hasAVX512()) in runOnMachineFunction()
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| D | X86ISelLowering.cpp | 206 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) in X86TargetLowering()
275 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) { in X86TargetLowering()
521 addRegisterClass(MVT::f32, Subtarget.hasAVX512() ? &X86::FR32XRegClass in X86TargetLowering()
523 addRegisterClass(MVT::f64, Subtarget.hasAVX512() ? &X86::FR64XRegClass in X86TargetLowering()
893 if (!Subtarget.hasAVX512()) in X86TargetLowering()
1028 if (!Subtarget.hasAVX512()) in X86TargetLowering()
1182 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) { in X86TargetLowering()
1425 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) { in X86TargetLowering()
1791 if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI()) in getPreferredVectorAction()
1805 if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI()) in getRegisterTypeForCallingConv()
[all …]
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| D | X86CallingConv.td | 122 CCIfSubtarget<"hasAVX512()",CCAssignToReg<RC.ZMM>>>,
196 CCIfSubtarget<"hasAVX512()", CCAssignToReg<RC.ZMM>>>
551 CCIfSubtarget<"hasAVX512()",
674 CCIfSubtarget<"hasAVX512()",
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| D | X86DomainReassignment.cpp | 739 if (!STI->hasAVX512()) in runOnMachineFunction()
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| D | X86SpeculativeLoadHardening.cpp | 1809 assert(Subtarget->hasAVX512() && "AVX512-specific register classes!"); in hardenLoadAddr()
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| D | X86InstrInfo.cpp | 2957 bool HasAVX512 = Subtarget.hasAVX512(); in CopyToFromAsymmetricReg()
3132 bool HasAVX512 = STI.hasAVX512(); in getLoadStoreRegOpcode()
3237 assert(STI.hasAVX512() && "Using 512-bit register requires AVX512"); in getLoadStoreRegOpcode()
6684 assert(Subtarget.hasAVX512() && "Requires AVX-512"); in setExecutionDomain()
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| D | X86InstrInfo.td | 829 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">;
830 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
831 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
832 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
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| /external/llvm/lib/Target/X86/ |
| D | X86Subtarget.h | 390 bool hasAVX512() const { return X86SSELevel >= AVX512F; } in hasAVX512() function
409 bool hasAnyFMA() const { return hasFMA() || hasFMA4() || hasAVX512(); } in hasAnyFMA()
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| D | X86RegisterInfo.cpp | 247 bool HasAVX512 = Subtarget.hasAVX512(); in getCalleeSavedRegs()
346 bool HasAVX512 = Subtarget.hasAVX512(); in getCallPreservedMask()
499 if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) { in getReservedRegs()
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| D | X86TargetTransformInfo.cpp | 49 if (Vector && ST->hasAVX512()) in getNumberOfRegisters()
58 if (ST->hasAVX512()) return 512; in getRegisterBitWidth()
143 if (ST->hasAVX512()) { in getArithmeticInstrCost()
840 if (ST->hasAVX512()) in getCastInstrCost()
923 if (ST->hasAVX512()) in getCmpSelInstrCost()
1173 if (!ST->hasAVX512()) in getMaskedMemoryOpCost()
1601 return DataWidth >= 32 && ST->hasAVX512(); in isLegalMaskedGather()
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| D | X86VZeroUpper.cpp | 260 if (!ST.hasAVX() || ST.hasAVX512() || ST.hasFastPartialYMMWrite()) in runOnMachineFunction()
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| D | X86FastISel.cpp | 458 assert(Subtarget->hasAVX512()); in X86FastEmitLoad()
466 assert(Subtarget->hasAVX512()); in X86FastEmitLoad()
477 assert(Subtarget->hasAVX512()); in X86FastEmitLoad()
605 assert(Subtarget->hasAVX512()); in X86FastEmitStore()
612 assert(Subtarget->hasAVX512()); in X86FastEmitStore()
622 assert(Subtarget->hasAVX512()); in X86FastEmitStore()
1415 if (I->getType()->isIntegerTy(1) && Subtarget->hasAVX512()) in X86SelectCmp()
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| D | X86ISelLowering.cpp | 169 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) in X86TargetLowering()
236 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) { in X86TargetLowering()
1128 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) { in X86TargetLowering()
1705 return Subtarget.hasAVX512() ? MVT::i1: MVT::i8; in getSetCCResultType()
1712 if (Subtarget.hasAVX512()) in getSetCCResultType()
2811 if (Subtarget.hasAVX512() && in LowerFormalArguments()
5817 bool hasRegVer = Subtarget.hasAVX512() && VT.is512BitVector() && in LowerVectorBroadcast()
6585 if (VT.getVectorElementType() == MVT::i1 && Subtarget.hasAVX512()) in LowerBUILD_VECTOR()
12024 assert(Subtarget.hasAVX512() && in lower512BitVectorShuffle()
12063 assert(Subtarget.hasAVX512() && in lower1BitVectorShuffle()
[all …]
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| D | X86InstrInfo.td | 795 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">,
797 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
798 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
799 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
828 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">;
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| D | X86CallingConv.td | 347 CCIfSubtarget<"hasAVX512()",
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| D | X86InstrInfo.cpp | 4341 bool HasAVX512 = Subtarget.hasAVX512(); in CopyToFromAsymmetricReg()
4453 bool HasAVX512 = Subtarget.hasAVX512(); in copyPhysReg()
4612 if (STI.hasAVX512()) { in getLoadStoreRegOpcode()
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