hasOpaqueSPAdjustment (reference) in projects: external

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Searched refs:hasOpaqueSPAdjustment (Results 1 – 25 of 169) sorted by relevance

12 3 4 5 6 7

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
D	leaFixup64.mir	`174 hasOpaqueSPAdjustment: false 209 hasOpaqueSPAdjustment: false 244 hasOpaqueSPAdjustment: false 278 hasOpaqueSPAdjustment: false 313 hasOpaqueSPAdjustment: false 348 hasOpaqueSPAdjustment: false 383 hasOpaqueSPAdjustment: false 419 hasOpaqueSPAdjustment: false 455 hasOpaqueSPAdjustment: false 490 hasOpaqueSPAdjustment: false [all …]`
D	leaFixup32.mir	`101 hasOpaqueSPAdjustment: false 136 hasOpaqueSPAdjustment: false 171 hasOpaqueSPAdjustment: false 206 hasOpaqueSPAdjustment: false 242 hasOpaqueSPAdjustment: false 278 hasOpaqueSPAdjustment: false 312 hasOpaqueSPAdjustment: false 348 hasOpaqueSPAdjustment: false 383 hasOpaqueSPAdjustment: false 418 hasOpaqueSPAdjustment: false [all …]`
D	domain-reassignment.mir	`103 hasOpaqueSPAdjustment: false 248 hasOpaqueSPAdjustment: false 367 hasOpaqueSPAdjustment: false 478 hasOpaqueSPAdjustment: false 581 hasOpaqueSPAdjustment: false 677 hasOpaqueSPAdjustment: false 747 hasOpaqueSPAdjustment: false 820 hasOpaqueSPAdjustment: false`
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MIR/Generic/
D	frame-info.mir	`41 # CHECK-NEXT: hasOpaqueSPAdjustment: false 71 # CHECK-NEXT: hasOpaqueSPAdjustment: true 86 hasOpaqueSPAdjustment: true`
/external/llvm/test/CodeGen/MIR/Generic/
D	frame-info.mir	`41 # CHECK-NEXT: hasOpaqueSPAdjustment: false 68 # CHECK-NEXT: hasOpaqueSPAdjustment: true 83 hasOpaqueSPAdjustment: true`
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
D	convert-rr-to-ri-instrs-out-of-range.mir	`242 hasOpaqueSPAdjustment: false 292 hasOpaqueSPAdjustment: false 348 hasOpaqueSPAdjustment: false 411 hasOpaqueSPAdjustment: false 470 hasOpaqueSPAdjustment: false 528 hasOpaqueSPAdjustment: false 590 hasOpaqueSPAdjustment: false 648 hasOpaqueSPAdjustment: false 707 hasOpaqueSPAdjustment: false 765 hasOpaqueSPAdjustment: false [all …]`
D	convert-rr-to-ri-instrs.mir	`1036 hasOpaqueSPAdjustment: false 1092 hasOpaqueSPAdjustment: false 1152 hasOpaqueSPAdjustment: false 1213 hasOpaqueSPAdjustment: false 1272 hasOpaqueSPAdjustment: false 1327 hasOpaqueSPAdjustment: false 1377 hasOpaqueSPAdjustment: false 1431 hasOpaqueSPAdjustment: false 1486 hasOpaqueSPAdjustment: false 1540 hasOpaqueSPAdjustment: false [all …]`
D	convert-rr-to-ri-instrs-R0-special-handling.mir	`111 hasOpaqueSPAdjustment: false 165 hasOpaqueSPAdjustment: false 219 hasOpaqueSPAdjustment: false 272 hasOpaqueSPAdjustment: false 322 hasOpaqueSPAdjustment: false 370 hasOpaqueSPAdjustment: false 417 hasOpaqueSPAdjustment: false`
D	rlwinm_rldicl_to_andi.mir	`107 hasOpaqueSPAdjustment: false 167 hasOpaqueSPAdjustment: false 227 hasOpaqueSPAdjustment: false 284 hasOpaqueSPAdjustment: false 338 hasOpaqueSPAdjustment: false 392 hasOpaqueSPAdjustment: false`
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
D	optimize-if-exec-masking.mir	`174 hasOpaqueSPAdjustment: false 232 hasOpaqueSPAdjustment: false 289 hasOpaqueSPAdjustment: false 348 hasOpaqueSPAdjustment: false 408 hasOpaqueSPAdjustment: false 468 hasOpaqueSPAdjustment: false 530 hasOpaqueSPAdjustment: false 590 hasOpaqueSPAdjustment: false 647 hasOpaqueSPAdjustment: false 704 hasOpaqueSPAdjustment: false`
D	shrink-vop3-carry-out.mir	`65 hasOpaqueSPAdjustment: false 149 hasOpaqueSPAdjustment: false 233 hasOpaqueSPAdjustment: false 316 hasOpaqueSPAdjustment: false 401 hasOpaqueSPAdjustment: false 486 hasOpaqueSPAdjustment: false`
D	fold-imm-f16-f32.mir	`149 hasOpaqueSPAdjustment: false 213 hasOpaqueSPAdjustment: false 280 hasOpaqueSPAdjustment: false 351 hasOpaqueSPAdjustment: false 418 hasOpaqueSPAdjustment: false 485 hasOpaqueSPAdjustment: false 555 hasOpaqueSPAdjustment: false 622 hasOpaqueSPAdjustment: false 688 hasOpaqueSPAdjustment: false`
D	constant-fold-imm-immreg.mir	`39 hasOpaqueSPAdjustment: false 124 hasOpaqueSPAdjustment: false 205 hasOpaqueSPAdjustment: false 310 hasOpaqueSPAdjustment: false 405 hasOpaqueSPAdjustment: false 513 hasOpaqueSPAdjustment: false 613 hasOpaqueSPAdjustment: false 722 hasOpaqueSPAdjustment: false`
D	merge-load-store-physreg.mir	`48 hasOpaqueSPAdjustment: false 95 hasOpaqueSPAdjustment: false`
/external/llvm/test/CodeGen/MIR/Lanai/
D	peephole-compare.mir	`205 hasOpaqueSPAdjustment: false 252 hasOpaqueSPAdjustment: false 300 hasOpaqueSPAdjustment: false 350 hasOpaqueSPAdjustment: false 400 hasOpaqueSPAdjustment: false 450 hasOpaqueSPAdjustment: false 500 hasOpaqueSPAdjustment: false 567 hasOpaqueSPAdjustment: false 662 hasOpaqueSPAdjustment: false`
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Lanai/
D	peephole-compare.mir	`201 hasOpaqueSPAdjustment: false 244 hasOpaqueSPAdjustment: false 288 hasOpaqueSPAdjustment: false 334 hasOpaqueSPAdjustment: false 380 hasOpaqueSPAdjustment: false 426 hasOpaqueSPAdjustment: false 472 hasOpaqueSPAdjustment: false 535 hasOpaqueSPAdjustment: false 626 hasOpaqueSPAdjustment: false`
/external/llvm/test/CodeGen/AMDGPU/
D	indirect-addressing-undef.mir	`83 hasOpaqueSPAdjustment: false 139 hasOpaqueSPAdjustment: false 194 hasOpaqueSPAdjustment: false 251 hasOpaqueSPAdjustment: false 307 hasOpaqueSPAdjustment: false`
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/micromips-sizereduction/
D	micromips-no-lwp-swp.mir	`42 hasOpaqueSPAdjustment: false 101 hasOpaqueSPAdjustment: false 160 hasOpaqueSPAdjustment: false 219 hasOpaqueSPAdjustment: false`
D	micromips-lwp-swp.mir	`44 hasOpaqueSPAdjustment: false 112 hasOpaqueSPAdjustment: false 180 hasOpaqueSPAdjustment: false 248 hasOpaqueSPAdjustment: false`
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
D	unaligned-memops-mapping.mir	`45 hasOpaqueSPAdjustment: false 91 hasOpaqueSPAdjustment: false`
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/longbranch/
D	branch-limits-int-micromipsr6.mir	`166 hasOpaqueSPAdjustment: false 253 hasOpaqueSPAdjustment: false 340 hasOpaqueSPAdjustment: false 427 hasOpaqueSPAdjustment: false 514 hasOpaqueSPAdjustment: false 601 hasOpaqueSPAdjustment: false 688 hasOpaqueSPAdjustment: false 775 hasOpaqueSPAdjustment: false 862 hasOpaqueSPAdjustment: false 949 hasOpaqueSPAdjustment: false [all …]`
D	branch-limits-int-mipsr6.mir	`166 hasOpaqueSPAdjustment: false 253 hasOpaqueSPAdjustment: false 340 hasOpaqueSPAdjustment: false 427 hasOpaqueSPAdjustment: false 514 hasOpaqueSPAdjustment: false 601 hasOpaqueSPAdjustment: false 688 hasOpaqueSPAdjustment: false 775 hasOpaqueSPAdjustment: false 862 hasOpaqueSPAdjustment: false 949 hasOpaqueSPAdjustment: false [all …]`
D	branch-limits-int-mips64r6.mir	`178 hasOpaqueSPAdjustment: false 255 hasOpaqueSPAdjustment: false 332 hasOpaqueSPAdjustment: false 430 hasOpaqueSPAdjustment: false 528 hasOpaqueSPAdjustment: false 626 hasOpaqueSPAdjustment: false 724 hasOpaqueSPAdjustment: false 822 hasOpaqueSPAdjustment: false 920 hasOpaqueSPAdjustment: false 1018 hasOpaqueSPAdjustment: false [all …]`
D	branch-limits-int-microMIPS.mir	`122 hasOpaqueSPAdjustment: false 213 hasOpaqueSPAdjustment: false 308 hasOpaqueSPAdjustment: false 403 hasOpaqueSPAdjustment: false 498 hasOpaqueSPAdjustment: false 593 hasOpaqueSPAdjustment: false 684 hasOpaqueSPAdjustment: false 779 hasOpaqueSPAdjustment: false`
D	branch-limits-int.mir	`100 hasOpaqueSPAdjustment: false 199 hasOpaqueSPAdjustment: false 298 hasOpaqueSPAdjustment: false 397 hasOpaqueSPAdjustment: false 496 hasOpaqueSPAdjustment: false 595 hasOpaqueSPAdjustment: false`

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