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Searched refs:hasSuperClassEq (Results 1 – 18 of 18) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp140 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
274 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
519 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || in optimizeAllLanesPattern()
520 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { in optimizeAllLanesPattern()
536 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { in optimizeAllLanesPattern()
542 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && in optimizeAllLanesPattern()
DThumb1InstrInfo.cpp112 assert((RC->hasSuperClassEq(&ARM::tGPRRegClass) || in loadRegFromStackSlot()
116 if (RC->hasSuperClassEq(&ARM::tGPRRegClass) || in loadRegFromStackSlot()
/external/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp142 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
280 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
531 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || in optimizeAllLanesPattern()
532 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { in optimizeAllLanesPattern()
548 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { in optimizeAllLanesPattern()
554 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && in optimizeAllLanesPattern()
/external/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp117 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
124 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
126 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp110 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
117 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
119 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86SpeculativeLoadHardening.cpp1769 if (!Subtarget->hasVLX() && (OpRC->hasSuperClassEq(&X86::VR128RegClass) || in hardenLoadAddr()
1770 OpRC->hasSuperClassEq(&X86::VR256RegClass))) { in hardenLoadAddr()
1772 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128RegClass); in hardenLoadAddr()
1806 } else if (OpRC->hasSuperClassEq(&X86::VR128XRegClass) || in hardenLoadAddr()
1807 OpRC->hasSuperClassEq(&X86::VR256XRegClass) || in hardenLoadAddr()
1808 OpRC->hasSuperClassEq(&X86::VR512RegClass)) { in hardenLoadAddr()
1810 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128XRegClass); in hardenLoadAddr()
1811 bool Is256Bit = OpRC->hasSuperClassEq(&X86::VR256XRegClass); in hardenLoadAddr()
1839 assert(OpRC->hasSuperClassEq(&X86::GR64RegClass) && in hardenLoadAddr()
1989 return RC->hasSuperClassEq(GPRRegClasses[Log2_32(RegBytes)]); in canHardenRegister()
DX86ISelLowering.cpp40401 return RC.hasSuperClassEq(&X86::GR8RegClass) || in isGRClass()
40402 RC.hasSuperClassEq(&X86::GR16RegClass) || in isGRClass()
40403 RC.hasSuperClassEq(&X86::GR32RegClass) || in isGRClass()
40404 RC.hasSuperClassEq(&X86::GR64RegClass) || in isGRClass()
40405 RC.hasSuperClassEq(&X86::LOW32_ADDR_ACCESS_RBPRegClass); in isGRClass()
40411 return RC.hasSuperClassEq(&X86::FR32XRegClass) || in isFRClass()
40412 RC.hasSuperClassEq(&X86::FR64XRegClass) || in isFRClass()
40413 RC.hasSuperClassEq(&X86::VR128XRegClass) || in isFRClass()
40414 RC.hasSuperClassEq(&X86::VR256XRegClass) || in isFRClass()
40415 RC.hasSuperClassEq(&X86::VR512RegClass); in isFRClass()
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetRegisterInfo.h161 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq() function
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp483 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitLoad()
505 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) && in PPCEmitLoad()
626 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitStore()
1187 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass); in SelectBinaryIntOp()
2012 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCMaterialize32BitInt()
DPPCInstrInfo.cpp158 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || in getOperandLatency()
159 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); in getOperandLatency()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.cpp257 if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) && in shouldCoalesce()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp487 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitLoad()
507 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) && in PPCEmitLoad()
641 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitStore()
1274 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass); in SelectBinaryIntOp()
2113 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCMaterialize32BitInt()
DPPCInstrInfo.cpp194 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || in getOperandLatency()
195 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); in getOperandLatency()
3099 MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ? in transformToImmForm()
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h161 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq() function
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h127 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq() function
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DMachineVerifier.cpp782 if (!RC->hasSuperClassEq(DRC)) { in visitMachineOperand()
/external/llvm/lib/CodeGen/
DMachineVerifier.cpp1043 if (!RC->hasSuperClassEq(DRC)) { in visitMachineOperand()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DMachineVerifier.cpp1307 if (!RC->hasSuperClassEq(DRC)) { in visitMachineOperand()