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Searched refs:imm4 (Results 1 – 22 of 22) sorted by relevance

/external/u-boot/arch/arm/include/asm/
Dopcodes-sec.h11 #define __SMC(imm4) __inst_arm_thumb32( \ argument
12 0xE1600070 | (((imm4) & 0xF) << 0), \
13 0xF7F08000 | (((imm4) & 0xF) << 16) \
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMips16InstrFormats.td271 // Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|>
281 bits<4> imm4;
289 let Inst{3-0} = imm4;
429 // <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0>
480 // <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0>
504 // <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0>
582 // <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0>
/external/llvm/lib/Target/Mips/
DMips16InstrFormats.td271 // Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|>
281 bits<4> imm4;
289 let Inst{3-0} = imm4;
429 // <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0>
480 // <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0>
504 // <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0>
582 // <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0>
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DSVEInstrFormats.td466 : I<(outs GPR64:$Rd), (ins sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
467 asm, "\t$Rd, $pattern, mul $imm4",
471 bits<4> imm4;
476 let Inst{19-16} = imm4;
493 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
494 asm, "\t$Zdn, $pattern, mul $imm4",
499 bits<4> imm4;
504 let Inst{19-16} = imm4;
525 : I<(outs GPR64:$Rdn), (ins GPR64:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
526 asm, "\t$Rdn, $pattern, mul $imm4",
[all …]
DAArch64InstrFormats.td6613 class BaseSIMDMov<bit Q, string size, bits<4> imm4, RegisterClass regtype,
6618 let Inst{14-11} = imm4;
/external/v8/src/arm/
Ddisasm-arm.cc2064 int imm4 = instr->Bits(11, 8); in DecodeSpecialCondition() local
2070 Vd, Vn, Vm, imm4); in DecodeSpecialCondition()
2230 int imm4 = instr->Bits(19, 16); in DecodeSpecialCondition() local
2232 if ((imm4 & 0x1) != 0) { in DecodeSpecialCondition()
2234 index = imm4 >> 1; in DecodeSpecialCondition()
2235 } else if ((imm4 & 0x2) != 0) { in DecodeSpecialCondition()
2237 index = imm4 >> 2; in DecodeSpecialCondition()
2240 index = imm4 >> 3; in DecodeSpecialCondition()
Dsimulator-arm.cc4569 int imm4 = instr->Bits(11, 8); in DecodeSpecialCondition() local
4576 int boundary = kSimd128Size - imm4; in DecodeSpecialCondition()
4579 dst[i] = src1[i + imm4]; in DecodeSpecialCondition()
4947 int imm4 = instr->Bits(19, 16); in DecodeSpecialCondition() local
4949 if ((imm4 & 0x1) != 0) { in DecodeSpecialCondition()
4951 index = imm4 >> 1; in DecodeSpecialCondition()
4953 } else if ((imm4 & 0x2) != 0) { in DecodeSpecialCondition()
4955 index = imm4 >> 2; in DecodeSpecialCondition()
4959 index = imm4 >> 3; in DecodeSpecialCondition()
Dassembler-arm.cc3183 int imm4 = (imm5 >> 1) & 0xF; in vcvt_f64_s32() local
3185 vd*B12 | 0x5*B9 | B8 | B7 | B6 | i*B5 | imm4); in vcvt_f64_s32()
4024 int imm4 = (1 << sz) | ((index << (sz + 1)) & 0xF); in EncodeNeonDupOp() local
4031 return 0x1E7U * B23 | d * B22 | 0x3 * B20 | imm4 * B16 | vd * B12 | in EncodeNeonDupOp()
/external/vixl/src/aarch64/
Dassembler-aarch64.h2127 void clrex(int imm4 = 0xf);
3767 static Instr CRm(int imm4) { in CRm() argument
3768 VIXL_ASSERT(IsUint4(imm4)); in CRm()
3769 return imm4 << CRm_offset; in CRm()
3772 static Instr CRn(int imm4) { in CRn() argument
3773 VIXL_ASSERT(IsUint4(imm4)); in CRn()
3774 return imm4 << CRn_offset; in CRn()
4021 static Instr ImmNEONExt(int imm4) { in ImmNEONExt() argument
4022 VIXL_ASSERT(IsUint4(imm4)); in ImmNEONExt()
4023 return imm4 << ImmNEONExt_offset; in ImmNEONExt()
[all …]
Ddisasm-aarch64.cc5283 unsigned imm4 = instr->GetImmNEON4(); in SubstituteImmediateField() local
5287 rn_index = imm4 >> tz; in SubstituteImmediateField()
Dsimulator-aarch64.cc4942 int imm4 = instr->GetImmNEON4(); in VisitNEONCopy() local
4943 int rn_index = imm4 >> tz; in VisitNEONCopy()
Dassembler-aarch64.cc2509 void Assembler::clrex(int imm4) { Emit(CLREX | CRm(imm4)); } in clrex() argument
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt371 # invalid imm4 value (0b1xxx)
372 # A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED;
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt371 # invalid imm4 value (0b1xxx)
372 # A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED;
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DREADME.txt78 | Ks4 | imm4 | |
/external/v8/src/arm64/
Dassembler-arm64.h3099 static Instr ImmNEONExt(int imm4) { in ImmNEONExt() argument
3100 DCHECK(is_uint4(imm4)); in ImmNEONExt()
3101 return imm4 << ImmNEONExt_offset; in ImmNEONExt()
3114 int imm4 = index << s; in ImmNEON4() local
3115 return imm4 << ImmNEON4_offset; in ImmNEON4()
Ddisasm-arm64.cc3705 unsigned imm4 = instr->ImmNEON4(); in SubstituteImmediateField() local
3709 rn_index = imm4 >> tz; in SubstituteImmediateField()
Dsimulator-arm64.cc4341 int imm4 = instr->ImmNEON4(); in VisitNEONCopy() local
4343 int rn_index = imm4 >> (lsb - 1); in VisitNEONCopy()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenMCCodeEmitter.inc5407 // op: imm4
8329 // op: imm4
9218 // op: imm4
11630 // op: imm4
11750 // op: imm4
11768 // op: imm4
/external/vixl/src/aarch32/
Dassembler-aarch32.cc17484 uint32_t imm4 = imm / dt.GetSize(); in vext() local
17486 rm.Encode(5, 0) | (imm4 << 8)); in vext()
17504 uint32_t imm4 = imm / dt.GetSize(); in vext() local
17506 rm.Encode(5, 0) | (imm4 << 8)); in vext()
17541 uint32_t imm4 = imm / dt.GetSize(); in vext() local
17543 rm.Encode(5, 0) | (imm4 << 8)); in vext()
17561 uint32_t imm4 = imm / dt.GetSize(); in vext() local
17563 rm.Encode(5, 0) | (imm4 << 8)); in vext()
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md269 void clrex(int imm4 = 0xf)
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td6161 class BaseSIMDMov<bit Q, string size, bits<4> imm4, RegisterClass regtype,
6166 let Inst{14-11} = imm4;