1//===- Mips16InstrFormats.td - Mips Instruction Formats ----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Describe MIPS instructions format 12// 13// CPU INSTRUCTION FORMATS 14// 15// funct or f Function field 16// 17// immediate 4-,5-,8- or 11-bit immediate, branch displacement, or 18// or imm address displacement 19// 20// op 5-bit major operation code 21// 22// rx 3-bit source or destination register 23// 24// ry 3-bit source or destination register 25// 26// rz 3-bit source or destination register 27// 28// sa 3- or 5-bit shift amount 29// 30//===----------------------------------------------------------------------===// 31 32 33// Base class for Mips 16 Format 34// This class does not depend on the instruction size 35// 36class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern, 37 InstrItinClass itin>: Instruction 38{ 39 40 let Namespace = "Mips"; 41 42 let OutOperandList = outs; 43 let InOperandList = ins; 44 45 let AsmString = asmstr; 46 let Pattern = pattern; 47 let Itinerary = itin; 48 49 let Predicates = [InMips16Mode]; 50} 51 52// 53// Generic Mips 16 Format 54// 55class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern, 56 InstrItinClass itin>: 57 MipsInst16_Base<outs, ins, asmstr, pattern, itin> 58{ 59 field bits<16> Inst; 60 bits<5> Opcode = 0; 61 62 // Top 5 bits are the 'opcode' field 63 let Inst{15-11} = Opcode; 64 65 let Size=2; 66 field bits<16> SoftFail = 0; 67} 68 69// 70// For 32 bit extended instruction forms. 71// 72class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern, 73 InstrItinClass itin>: 74 MipsInst16_Base<outs, ins, asmstr, pattern, itin> 75{ 76 field bits<32> Inst; 77 78 let Size=4; 79 field bits<32> SoftFail = 0; 80} 81 82class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern, 83 InstrItinClass itin>: 84 MipsInst16_32<outs, ins, asmstr, pattern, itin> 85{ 86 let Inst{31-27} = 0b11110; 87} 88 89 90 91// Mips Pseudo Instructions Format 92class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>: 93 MipsInst16<outs, ins, asmstr, pattern, IIPseudo> { 94 let isCodeGenOnly = 1; 95 let isPseudo = 1; 96} 97 98 99//===----------------------------------------------------------------------===// 100// Format I instruction class in Mips : <|opcode|imm11|> 101//===----------------------------------------------------------------------===// 102 103class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern, 104 InstrItinClass itin>: 105 MipsInst16<outs, ins, asmstr, pattern, itin> 106{ 107 bits<11> imm11; 108 109 let Opcode = op; 110 111 let Inst{10-0} = imm11; 112} 113 114//===----------------------------------------------------------------------===// 115// Format RI instruction class in Mips : <|opcode|rx|imm8|> 116//===----------------------------------------------------------------------===// 117 118class FRI16<bits<5> op, dag outs, dag ins, string asmstr, 119 list<dag> pattern, InstrItinClass itin>: 120 MipsInst16<outs, ins, asmstr, pattern, itin> 121{ 122 bits<3> rx; 123 bits<8> imm8; 124 125 let Opcode = op; 126 127 let Inst{10-8} = rx; 128 let Inst{7-0} = imm8; 129} 130 131//===----------------------------------------------------------------------===// 132// Format RR instruction class in Mips : <|opcode|rx|ry|funct|> 133//===----------------------------------------------------------------------===// 134 135class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr, 136 list<dag> pattern, InstrItinClass itin>: 137 MipsInst16<outs, ins, asmstr, pattern, itin> 138{ 139 bits<3> rx; 140 bits<3> ry; 141 bits<5> funct; 142 143 let Opcode = 0b11101; 144 let funct = _funct; 145 146 let Inst{10-8} = rx; 147 let Inst{7-5} = ry; 148 let Inst{4-0} = funct; 149} 150 151class FRRBreak16<dag outs, dag ins, string asmstr, 152 list<dag> pattern, InstrItinClass itin>: 153 MipsInst16<outs, ins, asmstr, pattern, itin> 154{ 155 bits<6> Code; 156 bits<5> funct; 157 158 let Opcode = 0b11101; 159 let funct = 0b00101; 160 161 let Inst{10-5} = Code; 162 let Inst{4-0} = funct; 163} 164 165// 166// For conversion functions. 167// 168class FRR_SF16<bits<5> _funct, bits<3> _subfunct, dag outs, dag ins, 169 string asmstr, list<dag> pattern, InstrItinClass itin>: 170 MipsInst16<outs, ins, asmstr, pattern, itin> 171{ 172 bits<3> rx; 173 bits<3> subfunct; 174 bits<5> funct; 175 176 let Opcode = 0b11101; // RR 177 let funct = _funct; 178 let subfunct = _subfunct; 179 180 let Inst{10-8} = rx; 181 let Inst{7-5} = subfunct; 182 let Inst{4-0} = funct; 183} 184 185// 186// just used for breakpoint (hardware and software) instructions. 187// 188class FC16<bits<5> _funct, dag outs, dag ins, string asmstr, 189 list<dag> pattern, InstrItinClass itin>: 190 MipsInst16<outs, ins, asmstr, pattern, itin> 191{ 192 bits<6> _code; // code is a keyword in tablegen 193 bits<5> funct; 194 195 let Opcode = 0b11101; // RR 196 let funct = _funct; 197 198 let Inst{10-5} = _code; 199 let Inst{4-0} = funct; 200} 201 202// 203// J(AL)R(C) subformat 204// 205class FRR16_JALRC<bits<1> _nd, bits<1> _l, bits<1> r_a, 206 dag outs, dag ins, string asmstr, 207 list<dag> pattern, InstrItinClass itin>: 208 MipsInst16<outs, ins, asmstr, pattern, itin> 209{ 210 bits<3> rx; 211 bits<1> nd; 212 bits<1> l; 213 bits<1> ra; 214 215 let nd = _nd; 216 let l = _l; 217 let ra = r_a; 218 219 let Opcode = 0b11101; 220 221 let Inst{10-8} = rx; 222 let Inst{7} = nd; 223 let Inst{6} = l; 224 let Inst{5} = ra; 225 let Inst{4-0} = 0; 226} 227 228//===----------------------------------------------------------------------===// 229// Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|> 230//===----------------------------------------------------------------------===// 231 232class FRRI16<bits<5> op, dag outs, dag ins, string asmstr, 233 list<dag> pattern, InstrItinClass itin>: 234 MipsInst16<outs, ins, asmstr, pattern, itin> 235{ 236 bits<3> rx; 237 bits<3> ry; 238 bits<5> imm5; 239 240 let Opcode = op; 241 242 243 let Inst{10-8} = rx; 244 let Inst{7-5} = ry; 245 let Inst{4-0} = imm5; 246} 247 248//===----------------------------------------------------------------------===// 249// Format RRR instruction class in Mips : <|opcode|rx|ry|rz|f|> 250//===----------------------------------------------------------------------===// 251 252class FRRR16<bits<2> _f, dag outs, dag ins, string asmstr, 253 list<dag> pattern, InstrItinClass itin>: 254 MipsInst16<outs, ins, asmstr, pattern, itin> 255{ 256 bits<3> rx; 257 bits<3> ry; 258 bits<3> rz; 259 bits<2> f; 260 261 let Opcode = 0b11100; 262 let f = _f; 263 264 let Inst{10-8} = rx; 265 let Inst{7-5} = ry; 266 let Inst{4-2} = rz; 267 let Inst{1-0} = f; 268} 269 270//===----------------------------------------------------------------------===// 271// Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|> 272//===----------------------------------------------------------------------===// 273 274class FRRI_A16<bits<1> _f, dag outs, dag ins, string asmstr, 275 list<dag> pattern, InstrItinClass itin>: 276 MipsInst16<outs, ins, asmstr, pattern, itin> 277{ 278 bits<3> rx; 279 bits<3> ry; 280 bits<1> f; 281 bits<4> imm4; 282 283 let Opcode = 0b01000; 284 let f = _f; 285 286 let Inst{10-8} = rx; 287 let Inst{7-5} = ry; 288 let Inst{4} = f; 289 let Inst{3-0} = imm4; 290} 291 292//===----------------------------------------------------------------------===// 293// Format Shift instruction class in Mips : <|opcode|rx|ry|sa|f|> 294//===----------------------------------------------------------------------===// 295 296class FSHIFT16<bits<2> _f, dag outs, dag ins, string asmstr, 297 list<dag> pattern, InstrItinClass itin>: 298 MipsInst16<outs, ins, asmstr, pattern, itin> 299{ 300 bits<3> rx; 301 bits<3> ry; 302 bits<3> sa; 303 bits<2> f; 304 305 let Opcode = 0b00110; 306 let f = _f; 307 308 let Inst{10-8} = rx; 309 let Inst{7-5} = ry; 310 let Inst{4-2} = sa; 311 let Inst{1-0} = f; 312} 313 314//===----------------------------------------------------------------------===// 315// Format i8 instruction class in Mips : <|opcode|funct|imm8> 316//===----------------------------------------------------------------------===// 317 318class FI816<bits<3> _func, dag outs, dag ins, string asmstr, 319 list<dag> pattern, InstrItinClass itin>: 320 MipsInst16<outs, ins, asmstr, pattern, itin> 321{ 322 bits<3> func; 323 bits<8> imm8; 324 325 let Opcode = 0b01100; 326 let func = _func; 327 328 let Inst{10-8} = func; 329 let Inst{7-0} = imm8; 330} 331 332//===----------------------------------------------------------------------===// 333// Format i8_MOVR32 instruction class in Mips : <|opcode|func|ry|r32> 334//===----------------------------------------------------------------------===// 335 336class FI8_MOVR3216<dag outs, dag ins, string asmstr, 337 list<dag> pattern, InstrItinClass itin>: 338 MipsInst16<outs, ins, asmstr, pattern, itin> 339{ 340 341 bits<4> ry; 342 bits<4> r32; 343 344 let Opcode = 0b01100; 345 346 let Inst{10-8} = 0b111; 347 let Inst{7-4} = ry; 348 let Inst{3-0} = r32; 349 350} 351 352 353 354//===----------------------------------------------------------------------===// 355// Format i8_MOV32R instruction class in Mips : <|opcode|func|r32|rz> 356//===----------------------------------------------------------------------===// 357 358class FI8_MOV32R16<dag outs, dag ins, string asmstr, 359 list<dag> pattern, InstrItinClass itin>: 360 MipsInst16<outs, ins, asmstr, pattern, itin> 361{ 362 363 bits<3> func; 364 bits<5> r32; 365 bits<3> rz; 366 367 368 let Opcode = 0b01100; 369 370 let Inst{10-8} = 0b101; 371 let Inst{7-5} = r32{2-0}; 372 let Inst{4-3} = r32{4-3}; 373 let Inst{2-0} = rz; 374 375} 376 377//===----------------------------------------------------------------------===// 378// Format i8_SVRS instruction class in Mips : 379// <|opcode|svrs|s|ra|s0|s1|framesize> 380//===----------------------------------------------------------------------===// 381 382class FI8_SVRS16<bits<1> _s, dag outs, dag ins, string asmstr, 383 list<dag> pattern, InstrItinClass itin>: 384 MipsInst16<outs, ins, asmstr, pattern, itin> 385{ 386 bits<1> s; 387 bits<1> ra = 0; 388 bits<1> s0 = 0; 389 bits<1> s1 = 0; 390 bits<4> framesize = 0; 391 392 let s =_s; 393 let Opcode = 0b01100; 394 395 let Inst{10-8} = 0b100; 396 let Inst{7} = s; 397 let Inst{6} = ra; 398 let Inst{5} = s0; 399 let Inst{4} = s1; 400 let Inst{3-0} = framesize; 401 402} 403 404//===----------------------------------------------------------------------===// 405// Format JAL instruction class in Mips16 : 406// <|opcode|svrs|s|ra|s0|s1|framesize> 407//===----------------------------------------------------------------------===// 408 409class FJAL16<bits<1> _X, dag outs, dag ins, string asmstr, 410 list<dag> pattern, InstrItinClass itin>: 411 MipsInst16_32<outs, ins, asmstr, pattern, itin> 412{ 413 bits<1> X; 414 bits<26> imm26; 415 416 417 let X = _X; 418 419 let Inst{31-27} = 0b00011; 420 let Inst{26} = X; 421 let Inst{25-21} = imm26{20-16}; 422 let Inst{20-16} = imm26{25-21}; 423 let Inst{15-0} = imm26{15-0}; 424 425} 426 427//===----------------------------------------------------------------------===// 428// Format EXT-I instruction class in Mips16 : 429// <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0> 430//===----------------------------------------------------------------------===// 431 432class FEXT_I16<bits<5> _eop, dag outs, dag ins, string asmstr, 433 list<dag> pattern, InstrItinClass itin>: 434 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin> 435{ 436 bits<16> imm16; 437 bits<5> eop; 438 439 let eop = _eop; 440 441 let Inst{26-21} = imm16{10-5}; 442 let Inst{20-16} = imm16{15-11}; 443 let Inst{15-11} = eop; 444 let Inst{10-5} = 0; 445 let Inst{4-0} = imm16{4-0}; 446 447} 448 449//===----------------------------------------------------------------------===// 450// Format ASMACRO instruction class in Mips16 : 451// <EXTEND|select|p4|p3|RRR|p2|p1|p0> 452//===----------------------------------------------------------------------===// 453 454class FASMACRO16<dag outs, dag ins, string asmstr, 455 list<dag> pattern, InstrItinClass itin>: 456 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin> 457{ 458 bits<3> select; 459 bits<3> p4; 460 bits<5> p3; 461 bits<5> RRR = 0b11100; 462 bits<3> p2; 463 bits<3> p1; 464 bits<5> p0; 465 466 467 let Inst{26-24} = select; 468 let Inst{23-21} = p4; 469 let Inst{20-16} = p3; 470 let Inst{15-11} = RRR; 471 let Inst{10-8} = p2; 472 let Inst{7-5} = p1; 473 let Inst{4-0} = p0; 474 475} 476 477 478//===----------------------------------------------------------------------===// 479// Format EXT-RI instruction class in Mips16 : 480// <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0> 481//===----------------------------------------------------------------------===// 482 483class FEXT_RI16<bits<5> _op, dag outs, dag ins, string asmstr, 484 list<dag> pattern, InstrItinClass itin>: 485 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin> 486{ 487 bits<16> imm16; 488 bits<5> op; 489 bits<3> rx; 490 491 let op = _op; 492 493 let Inst{26-21} = imm16{10-5}; 494 let Inst{20-16} = imm16{15-11}; 495 let Inst{15-11} = op; 496 let Inst{10-8} = rx; 497 let Inst{7-5} = 0; 498 let Inst{4-0} = imm16{4-0}; 499 500} 501 502//===----------------------------------------------------------------------===// 503// Format EXT-RRI instruction class in Mips16 : 504// <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0> 505//===----------------------------------------------------------------------===// 506 507class FEXT_RRI16<bits<5> _op, dag outs, dag ins, string asmstr, 508 list<dag> pattern, InstrItinClass itin>: 509 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin> 510{ 511 bits<5> op; 512 bits<16> imm16; 513 bits<3> rx; 514 bits<3> ry; 515 516 let op=_op; 517 518 let Inst{26-21} = imm16{10-5}; 519 let Inst{20-16} = imm16{15-11}; 520 let Inst{15-11} = op; 521 let Inst{10-8} = rx; 522 let Inst{7-5} = ry; 523 let Inst{4-0} = imm16{4-0}; 524 525} 526 527//===----------------------------------------------------------------------===// 528// Format EXT-RRI-A instruction class in Mips16 : 529// <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0> 530//===----------------------------------------------------------------------===// 531 532class FEXT_RRI_A16<bits<1> _f, dag outs, dag ins, string asmstr, 533 list<dag> pattern, InstrItinClass itin>: 534 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin> 535{ 536 bits<15> imm15; 537 bits<3> rx; 538 bits<3> ry; 539 bits<1> f; 540 541 let f = _f; 542 543 let Inst{26-20} = imm15{10-4}; 544 let Inst{19-16} = imm15{14-11}; 545 let Inst{15-11} = 0b01000; 546 let Inst{10-8} = rx; 547 let Inst{7-5} = ry; 548 let Inst{4} = f; 549 let Inst{3-0} = imm15{3-0}; 550 551} 552 553//===----------------------------------------------------------------------===// 554// Format EXT-SHIFT instruction class in Mips16 : 555// <|EXTEND|sa 4:0|s5|0|SHIFT|rx|ry|0|f> 556//===----------------------------------------------------------------------===// 557 558class FEXT_SHIFT16<bits<2> _f, dag outs, dag ins, string asmstr, 559 list<dag> pattern, InstrItinClass itin>: 560 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin> 561{ 562 bits<6> sa6; 563 bits<3> rx; 564 bits<3> ry; 565 bits<2> f; 566 567 let f = _f; 568 569 let Inst{26-22} = sa6{4-0}; 570 let Inst{21} = sa6{5}; 571 let Inst{20-16} = 0; 572 let Inst{15-11} = 0b00110; 573 let Inst{10-8} = rx; 574 let Inst{7-5} = ry; 575 let Inst{4-2} = 0; 576 let Inst{1-0} = f; 577 578} 579 580//===----------------------------------------------------------------------===// 581// Format EXT-I8 instruction class in Mips16 : 582// <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0> 583//===----------------------------------------------------------------------===// 584 585class FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr, 586 list<dag> pattern, InstrItinClass itin>: 587 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin> 588{ 589 bits<16> imm16; 590 bits<5> I8; 591 bits<3> funct; 592 593 let funct = _funct; 594 let I8 = 0b00110; 595 596 let Inst{26-21} = imm16{10-5}; 597 let Inst{20-16} = imm16{15-11}; 598 let Inst{15-11} = I8; 599 let Inst{10-8} = funct; 600 let Inst{7-5} = 0; 601 let Inst{4-0} = imm16{4-0}; 602 603} 604 605//===----------------------------------------------------------------------===// 606// Format EXT-I8_SVRS instruction class in Mips16 : 607// <|EXTEND|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0> 608//===----------------------------------------------------------------------===// 609 610class FEXT_I8_SVRS16<bits<1> s_, dag outs, dag ins, string asmstr, 611 list<dag> pattern, InstrItinClass itin>: 612 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin> 613{ 614 bits<3> xsregs =0; 615 bits<8> framesize =0; 616 bits<3> aregs =0; 617 bits<5> I8 = 0b01100; 618 bits<3> SVRS = 0b100; 619 bits<1> s; 620 bits<1> ra = 0; 621 bits<1> s0 = 0; 622 bits<1> s1 = 0; 623 624 let s= s_; 625 626 let Inst{26-24} = xsregs; 627 let Inst{23-20} = framesize{7-4}; 628 let Inst{19} = 0; 629 let Inst{18-16} = aregs; 630 let Inst{15-11} = I8; 631 let Inst{10-8} = SVRS; 632 let Inst{7} = s; 633 let Inst{6} = ra; 634 let Inst{5} = s0; 635 let Inst{4} = s1; 636 let Inst{3-0} = framesize{3-0}; 637 638 639} 640 641