/external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/ |
D | ldrex-strex.ll | 80 ; ***** Example of ldrexh ***** 81 ; ASM: ldrexh r1, [r2]
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/external/llvm/test/MC/ARM/ |
D | thumbv8m.s | 70 ldrexh r1, [r2] label
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D | basic-arm-instructions.s | 1194 ldrexh r2, [r5] 1199 @ CHECK: ldrexh r2, [r5] @ encoding: [0x9f,0x2f,0xf5,0xe1]
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D | basic-thumb2-instructions.s | 1057 ldrexh r9, [r12] 1064 @ CHECK: ldrexh r9, [r12] @ encoding: [0xdc,0xe8,0x5f,0x9f]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
D | thumbv8m.s | 70 ldrexh r1, [r2] label
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D | basic-arm-instructions.s | 1196 ldrexh r2, [r5] 1201 @ CHECK: ldrexh r2, [r5] @ encoding: [0x9f,0x2f,0xf5,0xe1]
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D | basic-thumb2-instructions.s | 1071 ldrexh r9, [r12] 1078 @ CHECK: ldrexh r9, [r12] @ encoding: [0xdc,0xe8,0x5f,0x9f]
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/external/llvm/test/CodeGen/ARM/ |
D | cmpxchg-O0.ll | 32 ; CHECK: ldrexh [[OLD:r[0-9]+]], [r0]
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D | ldstrex.ll | 47 ; CHECK: ldrexh r0, [r0]
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D | atomic-ops-v8.ll | 139 ; CHECK: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] 235 ; CHECK: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] 331 ; CHECK: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] 427 ; CHECK: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] 615 ; CHECK: ldrexh r[[OLD:[0-9]+]], {{.*}}[[ADDR]] 954 ; CHECK: ldrexh r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
D | cmpxchg-O0.ll | 35 ; CHECK: ldrexh [[OLD:r[0-9]+]], [r0]
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D | atomic-ops-v8.ll | 139 ; CHECK: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] 235 ; CHECK: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] 331 ; CHECK: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] 427 ; CHECK: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] 615 ; CHECK: ldrexh r[[OLD:[0-9]+]], {{.*}}[[ADDR]] 954 ; CHECK: ldrexh r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
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D | ldstrex.ll | 47 ; CHECK: ldrexh r0, [r0]
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/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
D | nacl-atomic-intrinsics.ll | 389 ; ARM32: ldrexh 668 ; ARM32: ldrexh 879 ; ARM32: ldrexh 921 ; ARM32: ldrexh r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}} 1118 ; ARM32: ldrexh 1288 ; ARM32: ldrexh 1449 ; ARM32: ldrexh 1618 ; ARM32: ldrexh [[V:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
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/external/v8/src/compiler/arm/ |
D | code-generator-arm.cc | 2692 ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(ldrexh, strexh); in AssembleArchInstruction() 2697 ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(ldrexh, strexh); in AssembleArchInstruction() 2723 ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER(ldrexh, strexh, in AssembleArchInstruction() 2731 ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER(ldrexh, strexh, in AssembleArchInstruction() 2753 ASSEMBLE_ATOMIC_BINOP(ldrexh, strexh, inst); \ in AssembleArchInstruction() 2758 ASSEMBLE_ATOMIC_BINOP(ldrexh, strexh, inst); \ in AssembleArchInstruction()
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/external/v8/src/arm/ |
D | assembler-arm.h | 931 void ldrexh(Register dst, Register src, Condition cond = al);
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/external/capstone/suite/MC/ARM/ |
D | basic-arm-instructions.s.cs | 329 0x9f,0x2f,0xf5,0xe1 = ldrexh r2, [r5]
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D | basic-thumb2-instructions.s.cs | 334 0xdc,0xe8,0x5f,0x9f = ldrexh r9, [r12]
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/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
D | basic-arm-instructions.s | 764 ldrexh r2, [r5] 769 @ CHECK: ldrexh r2, [r5] @ encoding: [0x9f,0x2f,0xf5,0xe1]
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D | basic-thumb2-instructions.s | 754 ldrexh r9, [r12] 761 @ CHECK: ldrexh r9, [r12] @ encoding: [0xdc,0xe8,0x5f,0x9f]
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/external/vixl/src/aarch32/ |
D | assembler-aarch32.h | 2478 void ldrexh(Condition cond, Register rt, const MemOperand& operand); 2479 void ldrexh(Register rt, const MemOperand& operand) { in ldrexh() function 2480 ldrexh(al, rt, operand); in ldrexh()
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D | disasm-aarch32.h | 860 void ldrexh(Condition cond, Register rt, const MemOperand& operand);
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/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
D | basic-arm-instructions.txt | 610 # CHECK: ldrexh r2, [r5]
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D | thumb2.txt | 633 # CHECK: ldrexh r9, [r12]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
D | basic-arm-instructions.txt | 691 # CHECK: ldrexh r2, [r5]
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