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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
Dset-at-directive.s10 # CHECK: lw $2, 0($1)
12 lw $2, 65536($2)
16 # CHECK: lw $1, 0($2)
18 lw $1, 65536($1)
22 # CHECK: lw $1, 0($3)
24 lw $1, 65536($1)
28 # CHECK: lw $1, 0($4)
30 lw $1, 65536($1)
34 # CHECK: lw $1, 0($5)
36 lw $1, 65536($1)
[all …]
Dmemory-offsets.s9 …lw $31, ($29) # CHECK: lw $ra, 0($sp) # encoding: [0x8f,0xbf,0x00,0x00]
10 …lw $31, 0($29) # CHECK: lw $ra, 0($sp) # encoding: [0x8f,0xbf,0x00,0x00]
11 …lw $31, (8)($29) # CHECK: lw $ra, 8($sp) # encoding: [0x8f,0xbf,0x00,0x08]
12 …lw $31, 3 + (4 * 8)($29) # CHECK: lw $ra, 35($sp) # encoding: [0x8f,0xbf,0x00,0x23]
13 …lw $31, (8 + 8)($29) # CHECK: lw $ra, 16($sp) # encoding: [0x8f,0xbf,0x00,0x10]
14 …lw $31, (8 << 4)($29) # CHECK: lw $ra, 128($sp) # encoding: [0x8f,0xbf,0x00,0x80]
15 …lw $31, (32768 >> 2)($29) # CHECK: lw $ra, 8192($sp) # encoding: [0x8f,0xbf,0x20,0x00]
16 …lw $31, 32768 >> 2($29) # CHECK: lw $ra, 8192($sp) # encoding: [0x8f,0xbf,0x20,0x00]
17 …lw $31, 2 << 3($29) # CHECK: lw $ra, 16($sp) # encoding: [0x8f,0xbf,0x00,0x10]
18 …lw $31, (2 << 3)($29) # CHECK: lw $ra, 16($sp) # encoding: [0x8f,0xbf,0x00,0x10]
[all …]
Dexpr1.s10 # 32R2-EL: lw $4, %lo(foo)($4) # encoding: [A,A,0x84,0x8c]
12 # 32R2-EL: lw $4, 56($4) # encoding: [0x38,0x00,0x84,0x8c]
16 # 32R2-EL: lw $4, %lo(foo+(%lo(8)))($1) # encoding: [A,A,0x24,0x8c]
18 # 32R2-EL: lw $4, %lo(12+foo)($4) # encoding: [A,A,0x84,0x8c]
20 # 32R2-EL: lw $4, %lo(16+foo)($4) # encoding: [A,A,0x84,0x8c]
22 # 32R2-EL: lw $4, 10($4) # encoding: [0x0a,0x00,0x84,0x8c]
23 # 32R2-EL: lw $4, 15($4) # encoding: [0x0f,0x00,0x84,0x8c]
24 # 32R2-EL: lw $4, 21($4) # encoding: [0x15,0x00,0x84,0x8c]
25 # 32R2-EL: lw $4, 28($4) # encoding: [0x1c,0x00,0x84,0x8c]
26 # 32R2-EL: lw $4, 6($4) # encoding: [0x06,0x00,0x84,0x8c]
[all …]
/external/llvm/test/MC/Mips/
Dset-at-directive.s10 # CHECK: lw $2, 0($1)
12 lw $2, 65536($2)
16 # CHECK: lw $1, 0($2)
18 lw $1, 65536($1)
22 # CHECK: lw $1, 0($3)
24 lw $1, 65536($1)
28 # CHECK: lw $1, 0($4)
30 lw $1, 65536($1)
34 # CHECK: lw $1, 0($5)
36 lw $1, 65536($1)
[all …]
Dexpr1.s10 # 32R2-EL: lw $4, %lo(foo)($4) # encoding: [A,A,0x84,0x8c]
12 # 32R2-EL: lw $4, 56($4) # encoding: [0x38,0x00,0x84,0x8c]
13 # 32R2-EL: lw $4, %lo(8+foo)($4) # encoding: [A,A,0x84,0x8c]
15 # 32R2-EL: lw $4, %lo(8+foo)($4) # encoding: [A,A,0x84,0x8c]
17 # 32R2-EL: lw $4, %lo(8+foo)($4) # encoding: [A,A,0x84,0x8c]
19 # 32R2-EL: lw $4, 10($4) # encoding: [0x0a,0x00,0x84,0x8c]
20 # 32R2-EL: lw $4, 15($4) # encoding: [0x0f,0x00,0x84,0x8c]
21 # 32R2-EL: lw $4, 21($4) # encoding: [0x15,0x00,0x84,0x8c]
22 # 32R2-EL: lw $4, 28($4) # encoding: [0x1c,0x00,0x84,0x8c]
23 # 32R2-EL: lw $4, %lo(65542)($4) # encoding: [0x06,0x00,0x84,0x8c]
[all …]
/external/llvm/test/CodeGen/Mips/
Dhf16_1.ll168 ; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_1)(${{[0-9]+}})
169 ; 2: lw ${{[0-9]+}}, %call16(v_sf)(${{[0-9]+}})
171 ; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_2)(${{[0-9]+}})
172 ; 2: lw ${{[0-9]+}}, %call16(v_df)(${{[0-9]+}})
174 ; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_5)(${{[0-9]+}})
175 ; 2: lw ${{[0-9]+}}, %call16(v_sf_sf)(${{[0-9]+}})
177 ; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_6)(${{[0-9]+}})
178 ; 2: lw ${{[0-9]+}}, %call16(v_df_sf)(${{[0-9]+}})
180 ; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_10)(${{[0-9]+}})
181 ; 2: lw ${{[0-9]+}}, %call16(v_df_df)(${{[0-9]+}})
[all …]
Dinlineasm_constraint_ZC.ll11 …call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [81…
13 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
15 ; ALL: lw $1, 0($[[BASEPTR]])
25 …call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [81…
27 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
29 ; ALL: lw $1, -4($[[BASEPTR]])
39 …call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [81…
41 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
43 ; ALL: lw $1, 4($[[BASEPTR]])
53 …call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [81…
[all …]
Dinterrupt-attr.ll38 ; CHECK: lw $26, [[R4:[0-9]+]]($sp)
40 ; CHECK: lw $26, [[R3:[0-9]+]]($sp)
42 ; CHECK: lw $1, {{[0-9]+}}($sp)
43 ; CHECK: lw $gp, {{[0-9]+}}($sp)
44 ; CHECK: lw $ra, [[R5:[0-9]+]]($sp)
45 ; CHECK: lw $8, {{[0-9]+}}($sp)
46 ; CHECK: lw $9, {{[0-9]+}}($sp)
47 ; CHECK: lw $10, {{[0-9]+}}($sp)
48 ; CHECK: lw $11, {{[0-9]+}}($sp)
49 ; CHECK: lw $12, {{[0-9]+}}($sp)
[all …]
Dfp16instrinsmc.ll113 ;pic: lw ${{[0-9]+}}, %call16(sinf)(${{[0-9]+}})
114 ;pic: lw ${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
127 ;pic: lw ${{[0-9]+}}, %call16(sin)(${{[0-9]+}})
128 ;pic: lw ${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
141 ;pic: lw ${{[0-9]+}}, %call16(cosf)(${{[0-9]+}})
142 ;pic: lw ${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
155 ;pic: lw ${{[0-9]+}}, %call16(cos)(${{[0-9]+}})
156 ;pic: lw ${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
169 ;pic: lw ${{[0-9]+}}, %call16(sqrtf)(${{[0-9]+}})
170 ;pic: lw ${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dhf16_1.ll168 ; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_1)(${{[0-9]+}})
169 ; 2: lw ${{[0-9]+}}, %call16(v_sf)(${{[0-9]+}})
171 ; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_2)(${{[0-9]+}})
172 ; 2: lw ${{[0-9]+}}, %call16(v_df)(${{[0-9]+}})
174 ; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_5)(${{[0-9]+}})
175 ; 2: lw ${{[0-9]+}}, %call16(v_sf_sf)(${{[0-9]+}})
177 ; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_6)(${{[0-9]+}})
178 ; 2: lw ${{[0-9]+}}, %call16(v_df_sf)(${{[0-9]+}})
180 ; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_10)(${{[0-9]+}})
181 ; 2: lw ${{[0-9]+}}, %call16(v_df_df)(${{[0-9]+}})
[all …]
Dinlineasm_constraint_ZC.ll11 …call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [81…
13 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
15 ; ALL: lw $1, 0($[[BASEPTR]])
25 …call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [81…
27 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
29 ; ALL: lw $1, -4($[[BASEPTR]])
39 …call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [81…
41 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
43 ; ALL: lw $1, 4($[[BASEPTR]])
53 …call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [81…
[all …]
Dinterrupt-attr.ll38 ; CHECK: lw $26, [[R4:[0-9]+]]($sp)
40 ; CHECK: lw $26, [[R3:[0-9]+]]($sp)
42 ; CHECK: lw $1, {{[0-9]+}}($sp)
43 ; CHECK: lw $gp, {{[0-9]+}}($sp)
44 ; CHECK: lw $ra, [[R5:[0-9]+]]($sp)
45 ; CHECK: lw $8, {{[0-9]+}}($sp)
46 ; CHECK: lw $9, {{[0-9]+}}($sp)
47 ; CHECK: lw $10, {{[0-9]+}}($sp)
48 ; CHECK: lw $11, {{[0-9]+}}($sp)
49 ; CHECK: lw $12, {{[0-9]+}}($sp)
[all …]
Dgprestore.ll25 ; O32-NEXT: lw $25, %call16(f1)($16)
28 ; O32-NEXT: lw $1, %got(p)($16)
29 ; O32-NEXT: lw $4, 0($1)
30 ; O32-NEXT: lw $25, %call16(f2)($16)
33 ; O32-NEXT: lw $1, %got(q)($16)
34 ; O32-NEXT: lw $17, 0($1)
35 ; O32-NEXT: lw $25, %call16(f2)($16)
38 ; O32-NEXT: lw $1, %got(r)($16)
39 ; O32-NEXT: lw $5, 0($1)
40 ; O32-NEXT: lw $25, %call16(f3)($16)
[all …]
Do32_cc_byval.ll23 ; CHECK-NEXT: lw $17, %got(f1.s1)($16)
25 ; CHECK-NEXT: lw $1, 12($18)
26 ; CHECK-NEXT: lw $2, 16($18)
27 ; CHECK-NEXT: lw $3, 20($18)
28 ; CHECK-NEXT: lw $4, 24($18)
29 ; CHECK-NEXT: lw $5, 28($18)
35 ; CHECK-NEXT: lw $1, 8($18)
37 ; CHECK-NEXT: lw $6, %lo(f1.s1)($17)
38 ; CHECK-NEXT: lw $7, 4($18)
39 ; CHECK-NEXT: lw $1, %got($CPI0_0)($16)
[all …]
Dfp16instrinsmc.ll113 ;pic: lw ${{[0-9]+}}, %call16(sinf)(${{[0-9]+}})
114 ;pic: lw ${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
127 ;pic: lw ${{[0-9]+}}, %call16(sin)(${{[0-9]+}})
128 ;pic: lw ${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
141 ;pic: lw ${{[0-9]+}}, %call16(cosf)(${{[0-9]+}})
142 ;pic: lw ${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
155 ;pic: lw ${{[0-9]+}}, %call16(cos)(${{[0-9]+}})
156 ;pic: lw ${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
169 ;pic: lw ${{[0-9]+}}, %call16(sqrtf)(${{[0-9]+}})
170 ;pic: lw ${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
[all …]
/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
Dvector-arg.ll32 ; MIPS32: lw v0,{{.*}}(sp)
33 ; MIPS32: lw v1,{{.*}}(sp)
56 ; MIPS32: lw v0,{{.*}}(sp)
57 ; MIPS32: lw v1,{{.*}}(sp)
58 ; MIPS32: lw a1,{{.*}}(sp)
59 ; MIPS32: lw a2,{{.*}}(sp)
82 ; MIPS32: lw v0,{{.*}}(sp)
83 ; MIPS32: lw v1,{{.*}}(sp)
84 ; MIPS32: lw a1,{{.*}}(sp)
85 ; MIPS32: lw a2,{{.*}}(sp)
[all …]
Dnop-insertion-no-vectors.ll34 ; MIPS32P50N1: lw {{.*}}
38 ; MIPS32P50N1: lw {{.*}}
44 ; MIPS32P50N1: lw {{.*}}
49 ; MIPS32P50N1: lw {{.*}}
53 ; MIPS32P50N1: lw {{.*}}
58 ; MIPS32P50N1: lw {{.*}}
61 ; MIPS32P50N1: lw {{.*}}
62 ; MIPS32P50N1: lw {{.*}}
66 ; MIPS32P50N1: lw {{.*}}
68 ; MIPS32P50N1: lw {{.*}}
[all …]
/external/eigen/bench/btl/data/
Dperlib_plot_settings.txt1 eigen3 ; with lines lw 4 lt 1 lc rgbcolor "black"
2 eigen2 ; with lines lw 3 lt 1 lc rgbcolor "#999999"
3 EigenBLAS ; with lines lw 3 lt 3 lc rgbcolor "#999999"
4 eigen3_novec ; with lines lw 2 lt 1 lc rgbcolor "#999999"
5 eigen3_nogccvec ; with lines lw 2 lt 2 lc rgbcolor "#991010"
6 INTEL_MKL ; with lines lw 3 lt 1 lc rgbcolor "#ff0000"
7 ATLAS ; with lines lw 3 lt 1 lc rgbcolor "#008000"
8 gmm ; with lines lw 3 lt 1 lc rgbcolor "#0000ff"
9 ublas ; with lines lw 3 lt 1 lc rgbcolor "#00b7ff"
10 mtl4 ; with lines lw 3 lt 1 lc rgbcolor "#d18847"
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/Fast-ISel/
Dicmpa.ll21 ; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
22 ; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
23 ; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
24 ; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
42 ; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
43 ; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
44 ; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
45 ; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
63 ; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
64 ; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
[all …]
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dicmpa.ll21 ; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
22 ; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
23 ; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
24 ; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
42 ; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
43 ; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
44 ; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
45 ; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
63 ; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
64 ; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/RISCV/
Dfp128.ll17 ; RV32I-NEXT: lw a1, %lo(y)(a0)
20 ; RV32I-NEXT: lw a2, %lo(x)(a1)
23 ; RV32I-NEXT: lw a2, 12(a0)
25 ; RV32I-NEXT: lw a2, 8(a0)
27 ; RV32I-NEXT: lw a0, 4(a0)
30 ; RV32I-NEXT: lw a1, 12(a0)
32 ; RV32I-NEXT: lw a1, 8(a0)
34 ; RV32I-NEXT: lw a0, 4(a0)
41 ; RV32I-NEXT: lw ra, 44(sp)
57 ; RV32I-NEXT: lw a1, %lo(y)(a0)
[all …]
Dremat.ll40 ; RV32I-NEXT: lw a0, %lo(a)(s3)
56 ; RV32I-NEXT: lw a1, %lo(l)(a1)
60 ; RV32I-NEXT: lw a4, %lo(e)(s1)
61 ; RV32I-NEXT: lw a3, %lo(d)(s8)
62 ; RV32I-NEXT: lw a2, %lo(c)(s2)
63 ; RV32I-NEXT: lw a1, %lo(b)(s4)
68 ; RV32I-NEXT: lw a0, %lo(k)(s5)
72 ; RV32I-NEXT: lw a4, %lo(f)(s10)
73 ; RV32I-NEXT: lw a3, %lo(e)(s1)
74 ; RV32I-NEXT: lw a2, %lo(d)(s8)
[all …]
Datomic-rmw.ll12 ; RV32I-NEXT: lw ra, 12(sp)
26 ; RV32I-NEXT: lw ra, 12(sp)
40 ; RV32I-NEXT: lw ra, 12(sp)
54 ; RV32I-NEXT: lw ra, 12(sp)
68 ; RV32I-NEXT: lw ra, 12(sp)
82 ; RV32I-NEXT: lw ra, 12(sp)
96 ; RV32I-NEXT: lw ra, 12(sp)
110 ; RV32I-NEXT: lw ra, 12(sp)
124 ; RV32I-NEXT: lw ra, 12(sp)
138 ; RV32I-NEXT: lw ra, 12(sp)
[all …]
Dframeaddr-returnaddr.ll17 ; RV32I-NEXT: lw s0, 8(sp)
18 ; RV32I-NEXT: lw ra, 12(sp)
32 ; RV32I-NEXT: lw a0, -8(s0)
33 ; RV32I-NEXT: lw a0, -8(a0)
34 ; RV32I-NEXT: lw s0, 8(sp)
35 ; RV32I-NEXT: lw ra, 12(sp)
51 ; RV32I-NEXT: lw a0, -8(s0)
52 ; RV32I-NEXT: lw a0, -8(a0)
53 ; RV32I-NEXT: lw a0, -8(a0)
54 ; RV32I-NEXT: lw s0, 104(sp)
[all …]
/external/libunwind_llvm/src/
DUnwindRegistersRestore.S870 lw $8, (4 * 33)($4)
872 lw $8, (4 * 34)($4)
875 lw $1, (4 * 1)($4)
876 lw $2, (4 * 2)($4)
877 lw $3, (4 * 3)($4)
879 lw $5, (4 * 5)($4)
880 lw $6, (4 * 6)($4)
881 lw $7, (4 * 7)($4)
882 lw $8, (4 * 8)($4)
883 lw $9, (4 * 9)($4)
[all …]

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