Searched refs:main_pll (Results 1 – 8 of 8) sorted by relevance
| /external/u-boot/arch/arm/mach-socfpga/ |
| D | clock_manager_s10.c | 26 writel(val, &clock_manager_base->main_pll.bypass); in cm_write_bypass_mainpll()
71 &clock_manager_base->main_pll.pllglob); in cm_basic_init()
72 writel(cfg->main_pll_fdbck, &clock_manager_base->main_pll.fdbck); in cm_basic_init()
73 writel(vcocalib, &clock_manager_base->main_pll.vcocalib); in cm_basic_init()
74 writel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0); in cm_basic_init()
75 writel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1); in cm_basic_init()
76 writel(cfg->main_pll_nocdiv, &clock_manager_base->main_pll.nocdiv); in cm_basic_init()
102 setbits_le32(&clock_manager_base->main_pll.pllglob, in cm_basic_init()
118 writel(0xff, &clock_manager_base->main_pll.mpuclk); in cm_basic_init()
119 writel(0xff, &clock_manager_base->main_pll.nocclk); in cm_basic_init()
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| D | clock_manager_gen5.c | 92 &clock_manager_base->main_pll.en); in cm_basic_init()
106 &clock_manager_base->main_pll.vco); in cm_basic_init()
124 &clock_manager_base->main_pll.l4src); in cm_basic_init()
127 readl(&clock_manager_base->main_pll.vco); in cm_basic_init()
136 writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco); in cm_basic_init()
147 writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk); in cm_basic_init()
153 writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk); in cm_basic_init()
156 writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk); in cm_basic_init()
160 &clock_manager_base->main_pll.cfgs2fuser0clk); in cm_basic_init()
169 writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk); in cm_basic_init()
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| D | clock_manager_arria10.c | 543 &clock_manager_base->main_pll.vco1); in cm_pll_ramp_main()
548 main_cfg->vco1_numer, &clock_manager_base->main_pll.vco1); in cm_pll_ramp_main()
630 &clock_manager_base->main_pll.enr); in cm_full_cfg()
637 &clock_manager_base->main_pll.bypasss); in cm_full_cfg()
649 &clock_manager_base->main_pll.vco0); in cm_full_cfg()
656 writel(CLKMGR_MAINPLL_VCO1_RESET, &clock_manager_base->main_pll.vco1); in cm_full_cfg()
682 &clock_manager_base->main_pll.vco1); in cm_full_cfg()
686 &clock_manager_base->main_pll.vco1); in cm_full_cfg()
712 clrbits_le32(&clock_manager_base->main_pll.vco0, in cm_full_cfg()
723 writel((readl(&clock_manager_base->main_pll.vco0) & in cm_full_cfg()
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| /external/u-boot/arch/arm/dts/ |
| D | socfpga_arria10.dtsi | 121 main_pll: main_pll@40 { label
133 clocks = <&main_pll>;
140 clocks = <&main_pll>;
147 clocks = <&main_pll>;
154 clocks = <&main_pll>;
161 clocks = <&main_pll>;
168 clocks = <&main_pll>;
176 clocks = <&main_pll>;
183 clocks = <&main_pll>;
190 clocks = <&main_pll>;
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| D | socfpga.dtsi | 134 main_pll: main_pll { label
145 clocks = <&main_pll>;
153 clocks = <&main_pll>;
161 clocks = <&main_pll>;
169 clocks = <&main_pll>;
176 clocks = <&main_pll>;
183 clocks = <&main_pll>;
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| /external/u-boot/arch/arm/mach-socfpga/include/mach/ |
| D | clock_manager_s10.h | 138 struct socfpga_clock_manager_main_pll main_pll; member
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| D | clock_manager_arria10.h | 86 struct socfpga_clock_manager_main_pll main_pll; member
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| D | clock_manager_gen5.h | 107 struct socfpga_clock_manager_main_pll main_pll; member
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