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Searched refs:movf (Results 1 – 25 of 136) sorted by relevance

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/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
Dvector-fcmp.ll28 ; MIPS32: movf [[R]],zero,$fcc0
31 ; MIPS32: movf [[R]],zero,$fcc0
34 ; MIPS32: movf [[R]],zero,$fcc0
37 ; MIPS32: movf [[R]],zero,$fcc0
64 ; MIPS32: movf [[R]],zero,$fcc0
67 ; MIPS32: movf [[R]],zero,$fcc0
70 ; MIPS32: movf [[R]],zero,$fcc0
73 ; MIPS32: movf [[R]],zero,$fcc0
130 ; MIPS32: movf [[R]],zero,$fcc0
133 ; MIPS32: movf [[R]],zero,$fcc0
[all …]
Dfp.cmp.ll80 ; MIPS32: movf [[REG]], $zero, {{.*}}
84 ; MIPS32: movf [[REG]], $zero, {{.*}}
255 ; MIPS32: movf [[REG]], $zero, {{.*}}
259 ; MIPS32: movf [[REG]], $zero, {{.*}}
310 ; MIPS32: movf [[REG]], $zero, {{.*}}
314 ; MIPS32: movf [[REG]], $zero, {{.*}}
418 ; MIPS32: movf [[REG]], $zero, {{.*}}
439 ; MIPS32: movf [[REG]], $zero, {{.*}}
539 ; MIPS32: movf [[REG]], $zero, {{.*}}
559 ; MIPS32: movf [[REG]], $zero, {{.*}}
[all …]
/external/llvm/test/MC/Mips/mips3/
Dinvalid-mips4.s12 …movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
13 … movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
14 …movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
15 … movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
16 …movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
17 … movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dinvalid-mips5.s13 …movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
14 … movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
15 …movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
16 … movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
17 …movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
18 … movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dfcmp.ll42 ; 32-C: movf $2, $zero, $fcc0
46 ; 64-C: movf $2, $zero, $fcc0
59 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
141 ; 32-C: movf $2, $zero, $fcc0
145 ; 64-C: movf $2, $zero, $fcc0
158 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
174 ; 32-C: movf $2, $zero, $fcc0
178 ; 64-C: movf $2, $zero, $fcc0
191 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
279 ; 32-C: movf $2, $zero, $fcc0
[all …]
Dselect.ll393 ; 32-NEXT: movf.s $f0, $f12, $fcc0
402 ; 32R2-NEXT: movf.s $f0, $f12, $fcc0
417 ; 64-NEXT: movf.s $f0, $f12, $fcc0
424 ; 64R2-NEXT: movf.s $f0, $f12, $fcc0
445 ; 32-NEXT: movf.d $f0, $f12, $fcc0
454 ; 32R2-NEXT: movf.d $f0, $f12, $fcc0
471 ; 64-NEXT: movf.d $f0, $f12, $fcc0
478 ; 64R2-NEXT: movf.d $f0, $f12, $fcc0
613 ; 32-NEXT: movf.d $f0, $f12, $fcc0
622 ; 32R2-NEXT: movf.d $f0, $f12, $fcc0
[all …]
/external/llvm/test/CodeGen/Mips/
Dfcmp.ll44 ; 32-C: movf $2, $zero, $fcc0
48 ; 64-C: movf $2, $zero, $fcc0
61 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
146 ; 32-C: movf $2, $zero, $fcc0
150 ; 64-C: movf $2, $zero, $fcc0
163 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
180 ; 32-C: movf $2, $zero, $fcc0
184 ; 64-C: movf $2, $zero, $fcc0
197 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
288 ; 32-C: movf $2, $zero, $fcc0
[all …]
Dselect.ll281 ; 32: movf.s $f14, $f12, $fcc0
287 ; 32R2: movf.s $f14, $f12, $fcc0
296 ; 64: movf.s $f13, $f12, $fcc0
300 ; 64R2: movf.s $f13, $f12, $fcc0
318 ; 32: movf.d $f14, $f12, $fcc0
324 ; 32R2: movf.d $f14, $f12, $fcc0
333 ; 64: movf.d $f13, $f12, $fcc0
337 ; 64R2: movf.d $f13, $f12, $fcc0
429 ; 32: movf.d $f14, $f12, $fcc0
435 ; 32R2: movf.d $f14, $f12, $fcc0
[all …]
/external/llvm/test/MC/Mips/
Dmicromips-movcond-instructions.s15 # CHECK-EL: movf $9, $6, $fcc0 # encoding: [0x26,0x55,0x7b,0x01]
22 # CHECK-EB: movf $9, $6, $fcc0 # encoding: [0x55,0x26,0x01,0x7b]
26 movf $9, $6, $fcc0
Dmips-fpu-instructions.s163 # CHECK: movf $2, $1, $fcc0 # encoding: [0x01,0x10,0x20,0x00]
166 # CHECK: movf.d $f4, $f6, $fcc2 # encoding: [0x11,0x31,0x28,0x46]
167 # CHECK: movf.s $f4, $f6, $fcc5 # encoding: [0x11,0x31,0x14,0x46]
198 movf $2, $1, $fcc0
201 movf.d $f4, $f6, $fcc2
202 movf.s $f4, $f6, $fcc5
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips32.s22 …movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
23 … movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
24 …movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
25 … movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
26 …movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
27 … movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dinvalid-mips32r2.s31 …movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
32 … movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
33 …movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
34 … movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
35 …movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
36 … movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dinvalid-mips5.s50 …movf $gp,$a0,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
51 … movf $gp,$a0,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
52 …movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
53 … movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
54 …movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
55 … movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dinvalid-mips4.s52 …movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
53 … movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
54 …movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
55 … movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
56 …movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
57 … movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
Dmicromips-movcond-instructions.s18 # CHECK-EL: movf $9, $6, $fcc0 # encoding: [0x26,0x55,0x7b,0x01]
29 # CHECK-EB: movf $9, $6, $fcc0 # encoding: [0x55,0x26,0x01,0x7b]
34 movf $9, $6, $fcc0
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips3/
Dinvalid-mips4.s12 …movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
13 …movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
14 …movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
15 …movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
16 …movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
17 …movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
Dinvalid-mips5.s13 …movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
14 …movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
15 …movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
16 …movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
17 …movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
18 …movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Dselect.ll51 ; CHECK: movf.s
60 ; CHECK: movf.d
87 ; CHECK: movf.d
96 ; CHECK: movf.s
123 ; CHECK: movf
154 ; CHECK: movf
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dselect-flt.ll198 ; CMOV-32: movf.s $f14, $f12, $fcc0
205 ; CMOV-64: movf.s $f13, $f12, $fcc0
212 ; MM32R3: movf.s $f14, $f12, $fcc0
235 ; CMOV-32: movf.s $f14, $f12, $fcc0
242 ; CMOV-64: movf.s $f13, $f12, $fcc0
249 ; MM32R3: movf.s $f14, $f12, $fcc0
309 ; CMOV-32: movf.s $f14, $f12, $fcc0
319 ; CMOV-64: movf.s $f13, $f12, $fcc0
329 ; MM32R3: movf.s $f14, $f12, $fcc0
Dselect-dbl.ll221 ; CMOV-32: movf.d $f14, $f12, $fcc0
228 ; CMOV-64: movf.d $f13, $f12, $fcc0
235 ; MM32R3: movf.d $f14, $f12, $fcc0
258 ; CMOV-32: movf.d $f14, $f12, $fcc0
265 ; CMOV-64: movf.d $f13, $f12, $fcc0
272 ; MM32R3: movf.d $f14, $f12, $fcc0
332 ; CMOV-32: movf.d $f14, $f12, $fcc0
342 ; CMOV-64: movf.d $f13, $f12, $fcc0
352 ; MM32R3: movf.d $f14, $f12, $fcc0
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips2/
Dinvalid-mips32.s23 …movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
24 …movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
25 …movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
26 …movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
27 …movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
28 …movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
Dinvalid-mips4.s52 …movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
53 …movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
54 …movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
55 …movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
56 …movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
57 …movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/external/swiftshader/third_party/subzero/tests_lit/assembler/mips32/
Dencoding_test_fcmp.ll102 ; ASM: movf $v0, $zero, $fcc0
109 ; DIS-NEXT: 28: 00001001 movf v0,zero,$fcc0
147 ; ASM: movf $v0, $zero, $fcc0
154 ; DIS-NEXT: 48: 00001001 movf v0,zero,$fcc0
372 ; ASM: movf $v0, $zero, $fcc0
379 ; DIS-NEXT: e8: 00001001 movf v0,zero,$fcc0
417 ; ASM: movf $v0, $zero, $fcc0
424 ; DIS-NEXT: 108: 00001001 movf v0,zero,$fcc0
462 ; ASM: movf $v0, $zero, $fcc0
469 ; DIS-NEXT: 128: 00001001 movf v0,zero,$fcc0
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips32.s14 …movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
15 …movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
16 …movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips32.s14 …movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
15 …movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
16 …movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…

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