1; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32 2; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32R2 3; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32R6 4; RUN: llc < %s -march=mips64el -mcpu=mips64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64 5; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64R2 6; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64R6 7 8@d2 = external global double 9@d3 = external global double 10 11define i32 @i32_icmp_ne_i32_val(i32 signext %s, i32 signext %f0, i32 signext %f1) nounwind readnone { 12entry: 13; ALL-LABEL: i32_icmp_ne_i32_val: 14 15; 32: movn $5, $6, $4 16; 32: move $2, $5 17 18; 32R2: movn $5, $6, $4 19; 32R2: move $2, $5 20 21; 32R6-DAG: seleqz $[[T0:[0-9]+]], $5, $4 22; 32R6-DAG: selnez $[[T1:[0-9]+]], $6, $4 23; 32R6: or $2, $[[T1]], $[[T0]] 24 25; 64: movn $5, $6, $4 26; 64: move $2, $5 27 28; 64R2: movn $5, $6, $4 29; 64R2: move $2, $5 30 31; 64R6-DAG: seleqz $[[T0:[0-9]+]], $5, $4 32; 64R6-DAG: selnez $[[T1:[0-9]+]], $6, $4 33; 64R6: or $2, $[[T1]], $[[T0]] 34 35 %tobool = icmp ne i32 %s, 0 36 %cond = select i1 %tobool, i32 %f1, i32 %f0 37 ret i32 %cond 38} 39 40define i64 @i32_icmp_ne_i64_val(i32 signext %s, i64 %f0, i64 %f1) nounwind readnone { 41entry: 42; ALL-LABEL: i32_icmp_ne_i64_val: 43 44; 32-DAG: lw $[[F1:[0-9]+]], 16($sp) 45; 32-DAG: movn $6, $[[F1]], $4 46; 32-DAG: lw $[[F1H:[0-9]+]], 20($sp) 47; 32: movn $7, $[[F1H]], $4 48; 32: move $2, $6 49; 32: move $3, $7 50 51; 32R2-DAG: lw $[[F1:[0-9]+]], 16($sp) 52; 32R2-DAG: movn $6, $[[F1]], $4 53; 32R2-DAG: lw $[[F1H:[0-9]+]], 20($sp) 54; 32R2: movn $7, $[[F1H]], $4 55; 32R2: move $2, $6 56; 32R2: move $3, $7 57 58; 32R6-DAG: lw $[[F1:[0-9]+]], 16($sp) 59; 32R6-DAG: seleqz $[[T0:[0-9]+]], $6, $4 60; 32R6-DAG: selnez $[[T1:[0-9]+]], $[[F1]], $4 61; 32R6: or $2, $[[T1]], $[[T0]] 62; 32R6-DAG: lw $[[F1H:[0-9]+]], 20($sp) 63; 32R6-DAG: seleqz $[[T0:[0-9]+]], $7, $4 64; 32R6-DAG: selnez $[[T1:[0-9]+]], $[[F1H]], $4 65; 32R6: or $3, $[[T1]], $[[T0]] 66 67; 64: movn $5, $6, $4 68; 64: move $2, $5 69 70; 64R2: movn $5, $6, $4 71; 64R2: move $2, $5 72 73; FIXME: This sll works around an implementation detail in the code generator 74; (setcc's result is i32 so bits 32-63 are undefined). It's not really 75; needed. 76; 64R6-DAG: sll $[[CC:[0-9]+]], $4, 0 77; 64R6-DAG: seleqz $[[T0:[0-9]+]], $5, $[[CC]] 78; 64R6-DAG: selnez $[[T1:[0-9]+]], $6, $[[CC]] 79; 64R6: or $2, $[[T1]], $[[T0]] 80 81 %tobool = icmp ne i32 %s, 0 82 %cond = select i1 %tobool, i64 %f1, i64 %f0 83 ret i64 %cond 84} 85 86define i64 @i64_icmp_ne_i64_val(i64 %s, i64 %f0, i64 %f1) nounwind readnone { 87entry: 88; ALL-LABEL: i64_icmp_ne_i64_val: 89 90; 32-DAG: or $[[CC:[0-9]+]], $4 91; 32-DAG: lw $[[F1:[0-9]+]], 16($sp) 92; 32-DAG: movn $6, $[[F1]], $[[CC]] 93; 32-DAG: lw $[[F1H:[0-9]+]], 20($sp) 94; 32: movn $7, $[[F1H]], $[[CC]] 95; 32: move $2, $6 96; 32: move $3, $7 97 98; 32R2-DAG: or $[[CC:[0-9]+]], $4 99; 32R2-DAG: lw $[[F1:[0-9]+]], 16($sp) 100; 32R2-DAG: movn $6, $[[F1]], $[[CC]] 101; 32R2-DAG: lw $[[F1H:[0-9]+]], 20($sp) 102; 32R2: movn $7, $[[F1H]], $[[CC]] 103; 32R2: move $2, $6 104; 32R2: move $3, $7 105 106; 32R6-DAG: lw $[[F1:[0-9]+]], 16($sp) 107; 32R6-DAG: or $[[T2:[0-9]+]], $4, $5 108; 32R6-DAG: seleqz $[[T0:[0-9]+]], $6, $[[T2]] 109; 32R6-DAG: selnez $[[T1:[0-9]+]], $[[F1]], $[[T2]] 110; 32R6: or $2, $[[T1]], $[[T0]] 111; 32R6-DAG: lw $[[F1H:[0-9]+]], 20($sp) 112; 32R6-DAG: seleqz $[[T0:[0-9]+]], $7, $[[T2]] 113; 32R6-DAG: selnez $[[T1:[0-9]+]], $[[F1H]], $[[T2]] 114; 32R6: or $3, $[[T1]], $[[T0]] 115 116; 64: movn $5, $6, $4 117; 64: move $2, $5 118 119; 64R2: movn $5, $6, $4 120; 64R2: move $2, $5 121 122; 64R6-DAG: seleqz $[[T0:[0-9]+]], $5, $4 123; 64R6-DAG: selnez $[[T1:[0-9]+]], $6, $4 124; 64R6: or $2, $[[T1]], $[[T0]] 125 126 %tobool = icmp ne i64 %s, 0 127 %cond = select i1 %tobool, i64 %f1, i64 %f0 128 ret i64 %cond 129} 130 131define float @i32_icmp_ne_f32_val(i32 signext %s, float %f0, float %f1) nounwind readnone { 132entry: 133; ALL-LABEL: i32_icmp_ne_f32_val: 134 135; 32-DAG: mtc1 $5, $[[F0:f[0-9]+]] 136; 32-DAG: mtc1 $6, $[[F1:f0]] 137; 32: movn.s $[[F1]], $[[F0]], $4 138 139; 32R2-DAG: mtc1 $5, $[[F0:f[0-9]+]] 140; 32R2-DAG: mtc1 $6, $[[F1:f0]] 141; 32R2: movn.s $[[F1]], $[[F0]], $4 142 143; 32R6-DAG: mtc1 $5, $[[F0:f[0-9]+]] 144; 32R6-DAG: mtc1 $6, $[[F1:f[0-9]+]] 145; 32R6: sltu $[[T0:[0-9]+]], $zero, $4 146; 32R6: mtc1 $[[T0]], $[[CC:f0]] 147; 32R6: sel.s $[[CC]], $[[F1]], $[[F0]] 148 149; 64: movn.s $f14, $f13, $4 150; 64: mov.s $f0, $f14 151 152; 64R2: movn.s $f14, $f13, $4 153; 64R2: mov.s $f0, $f14 154 155; 64R6: sltu $[[T0:[0-9]+]], $zero, $4 156; 64R6: mtc1 $[[T0]], $[[CC:f0]] 157; 64R6: sel.s $[[CC]], $f14, $f13 158 159 %tobool = icmp ne i32 %s, 0 160 %cond = select i1 %tobool, float %f0, float %f1 161 ret float %cond 162} 163 164define double @i32_icmp_ne_f64_val(i32 signext %s, double %f0, double %f1) nounwind readnone { 165entry: 166; ALL-LABEL: i32_icmp_ne_f64_val: 167 168; 32-DAG: mtc1 $6, $[[F0:f[1-3]*[02468]+]] 169; 32-DAG: mtc1 $7, $[[F0H:f[1-3]*[13579]+]] 170; 32-DAG: ldc1 $[[F1:f0]], 16($sp) 171; 32: movn.d $[[F1]], $[[F0]], $4 172 173; 32R2-DAG: mtc1 $6, $[[F0:f[0-9]+]] 174; 32R2-DAG: mthc1 $7, $[[F0]] 175; 32R2-DAG: ldc1 $[[F1:f0]], 16($sp) 176; 32R2: movn.d $[[F1]], $[[F0]], $4 177 178; 32R6-DAG: mtc1 $6, $[[F0:f[0-9]+]] 179; 32R6-DAG: mthc1 $7, $[[F0]] 180; 32R6-DAG: sltu $[[T0:[0-9]+]], $zero, $4 181; 32R6-DAG: mtc1 $[[T0]], $[[CC:f0]] 182; 32R6-DAG: ldc1 $[[F1:f[0-9]+]], 16($sp) 183; 32R6: sel.d $[[CC]], $[[F1]], $[[F0]] 184 185; 64: movn.d $f14, $f13, $4 186; 64: mov.d $f0, $f14 187 188; 64R2: movn.d $f14, $f13, $4 189; 64R2: mov.d $f0, $f14 190 191; 64R6-DAG: sltu $[[T0:[0-9]+]], $zero, $4 192; 64R6-DAG: mtc1 $[[T0]], $[[CC:f0]] 193; 64R6: sel.d $[[CC]], $f14, $f13 194 195 %tobool = icmp ne i32 %s, 0 196 %cond = select i1 %tobool, double %f0, double %f1 197 ret double %cond 198} 199 200define float @f32_fcmp_oeq_f32_val(float %f0, float %f1, float %f2, float %f3) nounwind readnone { 201entry: 202; ALL-LABEL: f32_fcmp_oeq_f32_val: 203 204; 32-DAG: mtc1 $6, $[[F2:f[0-9]+]] 205; 32-DAG: mtc1 $7, $[[F3:f[0-9]+]] 206; 32: c.eq.s $[[F2]], $[[F3]] 207; 32: movt.s $f14, $f12, $fcc0 208; 32: mov.s $f0, $f14 209 210; 32R2-DAG: mtc1 $6, $[[F2:f[0-9]+]] 211; 32R2-DAG: mtc1 $7, $[[F3:f[0-9]+]] 212; 32R2: c.eq.s $[[F2]], $[[F3]] 213; 32R2: movt.s $f14, $f12, $fcc0 214; 32R2: mov.s $f0, $f14 215 216; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]] 217; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]] 218; 32R6: cmp.eq.s $[[CC:f0]], $[[F2]], $[[F3]] 219; 32R6: sel.s $[[CC]], $f14, $f12 220 221; 64: c.eq.s $f14, $f15 222; 64: movt.s $f13, $f12, $fcc0 223; 64: mov.s $f0, $f13 224 225; 64R2: c.eq.s $f14, $f15 226; 64R2: movt.s $f13, $f12, $fcc0 227; 64R2: mov.s $f0, $f13 228 229; 64R6: cmp.eq.s $[[CC:f0]], $f14, $f15 230; 64R6: sel.s $[[CC]], $f13, $f12 231 232 %cmp = fcmp oeq float %f2, %f3 233 %cond = select i1 %cmp, float %f0, float %f1 234 ret float %cond 235} 236 237define float @f32_fcmp_olt_f32_val(float %f0, float %f1, float %f2, float %f3) nounwind readnone { 238entry: 239; ALL-LABEL: f32_fcmp_olt_f32_val: 240 241; 32-DAG: mtc1 $6, $[[F2:f[0-9]+]] 242; 32-DAG: mtc1 $7, $[[F3:f[0-9]+]] 243; 32: c.olt.s $[[F2]], $[[F3]] 244; 32: movt.s $f14, $f12, $fcc0 245; 32: mov.s $f0, $f14 246 247; 32R2-DAG: mtc1 $6, $[[F2:f[0-9]+]] 248; 32R2-DAG: mtc1 $7, $[[F3:f[0-9]+]] 249; 32R2: c.olt.s $[[F2]], $[[F3]] 250; 32R2: movt.s $f14, $f12, $fcc0 251; 32R2: mov.s $f0, $f14 252 253; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]] 254; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]] 255; 32R6: cmp.lt.s $[[CC:f0]], $[[F2]], $[[F3]] 256; 32R6: sel.s $[[CC]], $f14, $f12 257 258; 64: c.olt.s $f14, $f15 259; 64: movt.s $f13, $f12, $fcc0 260; 64: mov.s $f0, $f13 261 262; 64R2: c.olt.s $f14, $f15 263; 64R2: movt.s $f13, $f12, $fcc0 264; 64R2: mov.s $f0, $f13 265 266; 64R6: cmp.lt.s $[[CC:f0]], $f14, $f15 267; 64R6: sel.s $[[CC]], $f13, $f12 268 269 %cmp = fcmp olt float %f2, %f3 270 %cond = select i1 %cmp, float %f0, float %f1 271 ret float %cond 272} 273 274define float @f32_fcmp_ogt_f32_val(float %f0, float %f1, float %f2, float %f3) nounwind readnone { 275entry: 276; ALL-LABEL: f32_fcmp_ogt_f32_val: 277 278; 32-DAG: mtc1 $6, $[[F2:f[0-9]+]] 279; 32-DAG: mtc1 $7, $[[F3:f[0-9]+]] 280; 32: c.ule.s $[[F2]], $[[F3]] 281; 32: movf.s $f14, $f12, $fcc0 282; 32: mov.s $f0, $f14 283 284; 32R2-DAG: mtc1 $6, $[[F2:f[0-9]+]] 285; 32R2-DAG: mtc1 $7, $[[F3:f[0-9]+]] 286; 32R2: c.ule.s $[[F2]], $[[F3]] 287; 32R2: movf.s $f14, $f12, $fcc0 288; 32R2: mov.s $f0, $f14 289 290; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]] 291; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]] 292; 32R6: cmp.lt.s $[[CC:f0]], $[[F3]], $[[F2]] 293; 32R6: sel.s $[[CC]], $f14, $f12 294 295; 64: c.ule.s $f14, $f15 296; 64: movf.s $f13, $f12, $fcc0 297; 64: mov.s $f0, $f13 298 299; 64R2: c.ule.s $f14, $f15 300; 64R2: movf.s $f13, $f12, $fcc0 301; 64R2: mov.s $f0, $f13 302 303; 64R6: cmp.lt.s $[[CC:f0]], $f15, $f14 304; 64R6: sel.s $[[CC]], $f13, $f12 305 306 %cmp = fcmp ogt float %f2, %f3 307 %cond = select i1 %cmp, float %f0, float %f1 308 ret float %cond 309} 310 311define double @f32_fcmp_ogt_f64_val(double %f0, double %f1, float %f2, float %f3) nounwind readnone { 312entry: 313; ALL-LABEL: f32_fcmp_ogt_f64_val: 314 315; 32-DAG: lwc1 $[[F2:f[0-9]+]], 16($sp) 316; 32-DAG: lwc1 $[[F3:f[0-9]+]], 20($sp) 317; 32: c.ule.s $[[F2]], $[[F3]] 318; 32: movf.d $f14, $f12, $fcc0 319; 32: mov.d $f0, $f14 320 321; 32R2-DAG: lwc1 $[[F2:f[0-9]+]], 16($sp) 322; 32R2-DAG: lwc1 $[[F3:f[0-9]+]], 20($sp) 323; 32R2: c.ule.s $[[F2]], $[[F3]] 324; 32R2: movf.d $f14, $f12, $fcc0 325; 32R2: mov.d $f0, $f14 326 327; 32R6-DAG: lwc1 $[[F2:f[0-9]+]], 16($sp) 328; 32R6-DAG: lwc1 $[[F3:f[0-9]+]], 20($sp) 329; 32R6: cmp.lt.s $[[CC:f0]], $[[F3]], $[[F2]] 330; 32R6: sel.d $[[CC]], $f14, $f12 331 332; 64: c.ule.s $f14, $f15 333; 64: movf.d $f13, $f12, $fcc0 334; 64: mov.d $f0, $f13 335 336; 64R2: c.ule.s $f14, $f15 337; 64R2: movf.d $f13, $f12, $fcc0 338; 64R2: mov.d $f0, $f13 339 340; 64R6: cmp.lt.s $[[CC:f0]], $f15, $f14 341; 64R6: sel.d $[[CC]], $f13, $f12 342 343 %cmp = fcmp ogt float %f2, %f3 344 %cond = select i1 %cmp, double %f0, double %f1 345 ret double %cond 346} 347 348define double @f64_fcmp_oeq_f64_val(double %f0, double %f1, double %f2, double %f3) nounwind readnone { 349entry: 350; ALL-LABEL: f64_fcmp_oeq_f64_val: 351 352; 32-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp) 353; 32-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp) 354; 32: c.eq.d $[[F2]], $[[F3]] 355; 32: movt.d $f14, $f12, $fcc0 356; 32: mov.d $f0, $f14 357 358; 32R2-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp) 359; 32R2-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp) 360; 32R2: c.eq.d $[[F2]], $[[F3]] 361; 32R2: movt.d $f14, $f12, $fcc0 362; 32R2: mov.d $f0, $f14 363 364; 32R6-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp) 365; 32R6-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp) 366; 32R6: cmp.eq.d $[[CC:f0]], $[[F2]], $[[F3]] 367; 32R6: sel.d $[[CC]], $f14, $f12 368 369; 64: c.eq.d $f14, $f15 370; 64: movt.d $f13, $f12, $fcc0 371; 64: mov.d $f0, $f13 372 373; 64R2: c.eq.d $f14, $f15 374; 64R2: movt.d $f13, $f12, $fcc0 375; 64R2: mov.d $f0, $f13 376 377; 64R6: cmp.eq.d $[[CC:f0]], $f14, $f15 378; 64R6: sel.d $[[CC]], $f13, $f12 379 380 %cmp = fcmp oeq double %f2, %f3 381 %cond = select i1 %cmp, double %f0, double %f1 382 ret double %cond 383} 384 385define double @f64_fcmp_olt_f64_val(double %f0, double %f1, double %f2, double %f3) nounwind readnone { 386entry: 387; ALL-LABEL: f64_fcmp_olt_f64_val: 388 389; 32-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp) 390; 32-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp) 391; 32: c.olt.d $[[F2]], $[[F3]] 392; 32: movt.d $f14, $f12, $fcc0 393; 32: mov.d $f0, $f14 394 395; 32R2-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp) 396; 32R2-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp) 397; 32R2: c.olt.d $[[F2]], $[[F3]] 398; 32R2: movt.d $f14, $f12, $fcc0 399; 32R2: mov.d $f0, $f14 400 401; 32R6-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp) 402; 32R6-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp) 403; 32R6: cmp.lt.d $[[CC:f0]], $[[F2]], $[[F3]] 404; 32R6: sel.d $[[CC]], $f14, $f12 405 406; 64: c.olt.d $f14, $f15 407; 64: movt.d $f13, $f12, $fcc0 408; 64: mov.d $f0, $f13 409 410; 64R2: c.olt.d $f14, $f15 411; 64R2: movt.d $f13, $f12, $fcc0 412; 64R2: mov.d $f0, $f13 413 414; 64R6: cmp.lt.d $[[CC:f0]], $f14, $f15 415; 64R6: sel.d $[[CC]], $f13, $f12 416 417 %cmp = fcmp olt double %f2, %f3 418 %cond = select i1 %cmp, double %f0, double %f1 419 ret double %cond 420} 421 422define double @f64_fcmp_ogt_f64_val(double %f0, double %f1, double %f2, double %f3) nounwind readnone { 423entry: 424; ALL-LABEL: f64_fcmp_ogt_f64_val: 425 426; 32-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp) 427; 32-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp) 428; 32: c.ule.d $[[F2]], $[[F3]] 429; 32: movf.d $f14, $f12, $fcc0 430; 32: mov.d $f0, $f14 431 432; 32R2-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp) 433; 32R2-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp) 434; 32R2: c.ule.d $[[F2]], $[[F3]] 435; 32R2: movf.d $f14, $f12, $fcc0 436; 32R2: mov.d $f0, $f14 437 438; 32R6-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp) 439; 32R6-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp) 440; 32R6: cmp.lt.d $[[CC:f0]], $[[F3]], $[[F2]] 441; 32R6: sel.d $[[CC]], $f14, $f12 442 443; 64: c.ule.d $f14, $f15 444; 64: movf.d $f13, $f12, $fcc0 445; 64: mov.d $f0, $f13 446 447; 64R2: c.ule.d $f14, $f15 448; 64R2: movf.d $f13, $f12, $fcc0 449; 64R2: mov.d $f0, $f13 450 451; 64R6: cmp.lt.d $[[CC:f0]], $f15, $f14 452; 64R6: sel.d $[[CC]], $f13, $f12 453 454 %cmp = fcmp ogt double %f2, %f3 455 %cond = select i1 %cmp, double %f0, double %f1 456 ret double %cond 457} 458 459define float @f64_fcmp_ogt_f32_val(float %f0, float %f1, double %f2, double %f3) nounwind readnone { 460entry: 461; ALL-LABEL: f64_fcmp_ogt_f32_val: 462 463; 32-DAG: mtc1 $6, $[[F2:f[1-3]*[02468]+]] 464; 32-DAG: mtc1 $7, $[[F2H:f[1-3]*[13579]+]] 465; 32-DAG: ldc1 $[[F3:f[0-9]+]], 16($sp) 466; 32: c.ule.d $[[F2]], $[[F3]] 467; 32: movf.s $f14, $f12, $fcc0 468; 32: mov.s $f0, $f14 469 470; 32R2-DAG: mtc1 $6, $[[F2:f[0-9]+]] 471; 32R2-DAG: mthc1 $7, $[[F2]] 472; 32R2-DAG: ldc1 $[[F3:f[0-9]+]], 16($sp) 473; 32R2: c.ule.d $[[F2]], $[[F3]] 474; 32R2: movf.s $f14, $f12, $fcc0 475; 32R2: mov.s $f0, $f14 476 477; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]] 478; 32R6-DAG: mthc1 $7, $[[F2]] 479; 32R6-DAG: ldc1 $[[F3:f[0-9]+]], 16($sp) 480; 32R6: cmp.lt.d $[[CC:f0]], $[[F3]], $[[F2]] 481; 32R6: sel.s $[[CC]], $f14, $f12 482 483; 64: c.ule.d $f14, $f15 484; 64: movf.s $f13, $f12, $fcc0 485; 64: mov.s $f0, $f13 486 487; 64R2: c.ule.d $f14, $f15 488; 64R2: movf.s $f13, $f12, $fcc0 489; 64R2: mov.s $f0, $f13 490 491; 64R6: cmp.lt.d $[[CC:f0]], $f15, $f14 492; 64R6: sel.s $[[CC]], $f13, $f12 493 494 %cmp = fcmp ogt double %f2, %f3 495 %cond = select i1 %cmp, float %f0, float %f1 496 ret float %cond 497} 498 499define i32 @f32_fcmp_oeq_i32_val(i32 signext %f0, i32 signext %f1, float %f2, float %f3) nounwind readnone { 500entry: 501; ALL-LABEL: f32_fcmp_oeq_i32_val: 502 503; 32-DAG: mtc1 $6, $[[F2:f[0-9]+]] 504; 32-DAG: mtc1 $7, $[[F3:f[0-9]+]] 505; 32: c.eq.s $[[F2]], $[[F3]] 506; 32: movt $5, $4, $fcc0 507; 32: move $2, $5 508 509; 32R2-DAG: mtc1 $6, $[[F2:f[0-9]+]] 510; 32R2-DAG: mtc1 $7, $[[F3:f[0-9]+]] 511; 32R2: c.eq.s $[[F2]], $[[F3]] 512; 32R2: movt $5, $4, $fcc0 513; 32R2: move $2, $5 514 515; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]] 516; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]] 517; 32R6: cmp.eq.s $[[CC:f[0-9]+]], $[[F2]], $[[F3]] 518; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]] 519; 32R6: andi $[[CCGPR]], $[[CCGPR]], 1 520; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]] 521; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]] 522; 32R6: or $2, $[[NE]], $[[EQ]] 523 524; 64: c.eq.s $f14, $f15 525; 64: movt $5, $4, $fcc0 526; 64: move $2, $5 527 528; 64R2: c.eq.s $f14, $f15 529; 64R2: movt $5, $4, $fcc0 530; 64R2: move $2, $5 531 532; 64R6: cmp.eq.s $[[CC:f[0-9]+]], $f14, $f15 533; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]] 534; 64R6: andi $[[CCGPR]], $[[CCGPR]], 1 535; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]] 536; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]] 537; 64R6: or $2, $[[NE]], $[[EQ]] 538 539 %cmp = fcmp oeq float %f2, %f3 540 %cond = select i1 %cmp, i32 %f0, i32 %f1 541 ret i32 %cond 542} 543 544define i32 @f32_fcmp_olt_i32_val(i32 signext %f0, i32 signext %f1, float %f2, float %f3) nounwind readnone { 545entry: 546; ALL-LABEL: f32_fcmp_olt_i32_val: 547 548; 32-DAG: mtc1 $6, $[[F2:f[0-9]+]] 549; 32-DAG: mtc1 $7, $[[F3:f[0-9]+]] 550; 32: c.olt.s $[[F2]], $[[F3]] 551; 32: movt $5, $4, $fcc0 552; 32: move $2, $5 553 554; 32R2-DAG: mtc1 $6, $[[F2:f[0-9]+]] 555; 32R2-DAG: mtc1 $7, $[[F3:f[0-9]+]] 556; 32R2: c.olt.s $[[F2]], $[[F3]] 557; 32R2: movt $5, $4, $fcc0 558; 32R2: move $2, $5 559 560; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]] 561; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]] 562; 32R6: cmp.lt.s $[[CC:f[0-9]+]], $[[F2]], $[[F3]] 563; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]] 564; 32R6: andi $[[CCGPR]], $[[CCGPR]], 1 565; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]] 566; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]] 567; 32R6: or $2, $[[NE]], $[[EQ]] 568 569; 64: c.olt.s $f14, $f15 570; 64: movt $5, $4, $fcc0 571; 64: move $2, $5 572 573; 64R2: c.olt.s $f14, $f15 574; 64R2: movt $5, $4, $fcc0 575; 64R2: move $2, $5 576 577; 64R6: cmp.lt.s $[[CC:f[0-9]+]], $f14, $f15 578; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]] 579; 64R6: andi $[[CCGPR]], $[[CCGPR]], 1 580; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]] 581; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]] 582; 64R6: or $2, $[[NE]], $[[EQ]] 583 %cmp = fcmp olt float %f2, %f3 584 %cond = select i1 %cmp, i32 %f0, i32 %f1 585 ret i32 %cond 586} 587 588define i32 @f32_fcmp_ogt_i32_val(i32 signext %f0, i32 signext %f1, float %f2, float %f3) nounwind readnone { 589entry: 590; ALL-LABEL: f32_fcmp_ogt_i32_val: 591 592; 32-DAG: mtc1 $6, $[[F2:f[0-9]+]] 593; 32-DAG: mtc1 $7, $[[F3:f[0-9]+]] 594; 32: c.ule.s $[[F2]], $[[F3]] 595; 32: movf $5, $4, $fcc0 596; 32: move $2, $5 597 598; 32R2-DAG: mtc1 $6, $[[F2:f[0-9]+]] 599; 32R2-DAG: mtc1 $7, $[[F3:f[0-9]+]] 600; 32R2: c.ule.s $[[F2]], $[[F3]] 601; 32R2: movf $5, $4, $fcc0 602; 32R2: move $2, $5 603 604; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]] 605; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]] 606; 32R6: cmp.lt.s $[[CC:f[0-9]+]], $[[F3]], $[[F2]] 607; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]] 608; 32R6: andi $[[CCGPR]], $[[CCGPR]], 1 609; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]] 610; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]] 611; 32R6: or $2, $[[NE]], $[[EQ]] 612 613; 64: c.ule.s $f14, $f15 614; 64: movf $5, $4, $fcc0 615; 64: move $2, $5 616 617; 64R2: c.ule.s $f14, $f15 618; 64R2: movf $5, $4, $fcc0 619; 64R2: move $2, $5 620 621; 64R6: cmp.lt.s $[[CC:f[0-9]+]], $f15, $f14 622; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]] 623; 64R6: andi $[[CCGPR]], $[[CCGPR]], 1 624; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]] 625; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]] 626; 64R6: or $2, $[[NE]], $[[EQ]] 627 628 %cmp = fcmp ogt float %f2, %f3 629 %cond = select i1 %cmp, i32 %f0, i32 %f1 630 ret i32 %cond 631} 632 633define i32 @f64_fcmp_oeq_i32_val(i32 signext %f0, i32 signext %f1) nounwind readonly { 634entry: 635; ALL-LABEL: f64_fcmp_oeq_i32_val: 636 637; 32-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp) 638; 32-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25 639; 32-DAG: lw $[[D2:[0-9]+]], %got(d2)($1) 640; 32-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]]) 641; 32-DAG: lw $[[D3:[0-9]+]], %got(d3)($1) 642; 32-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 643; 32: c.eq.d $[[TMP]], $[[TMP1]] 644; 32: movt $5, $4, $fcc0 645; 32: move $2, $5 646 647; 32R2-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp) 648; 32R2-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25 649; 32R2-DAG: lw $[[D2:[0-9]+]], %got(d2)($1) 650; 32R2-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]]) 651; 32R2-DAG: lw $[[D3:[0-9]+]], %got(d3)($1) 652; 32R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 653; 32R2: c.eq.d $[[TMP]], $[[TMP1]] 654; 32R2: movt $5, $4, $fcc0 655; 32R2: move $2, $5 656 657; 32R6-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp) 658; 32R6-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25 659; 32R6-DAG: lw $[[D2:[0-9]+]], %got(d2)($1) 660; 32R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]]) 661; 32R6-DAG: lw $[[D3:[0-9]+]], %got(d3)($1) 662; 32R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 663; 32R6: cmp.eq.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]] 664; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]] 665; 32R6: andi $[[CCGPR]], $[[CCGPR]], 1 666; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]] 667; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]] 668; 32R6: or $2, $[[NE]], $[[EQ]] 669 670; 64-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val))) 671; 64-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25 672; 64-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1) 673; 64-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]]) 674; 64-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1) 675; 64-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 676; 64: c.eq.d $[[TMP]], $[[TMP1]] 677; 64: movt $5, $4, $fcc0 678; 64: move $2, $5 679 680; 64R2-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val))) 681; 64R2-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25 682; 64R2-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1) 683; 64R2-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]]) 684; 64R2-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1) 685; 64R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 686; 64R2: c.eq.d $[[TMP]], $[[TMP1]] 687; 64R2: movt $5, $4, $fcc0 688; 64R2: move $2, $5 689 690; 64R6-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val))) 691; 64R6-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25 692; 64R6-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1) 693; 64R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]]) 694; 64R6-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1) 695; 64R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 696; 64R6: cmp.eq.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]] 697; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]] 698; 64R6: andi $[[CCGPR]], $[[CCGPR]], 1 699; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]] 700; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]] 701; 64R6: or $2, $[[NE]], $[[EQ]] 702 703 %tmp = load double, double* @d2, align 8 704 %tmp1 = load double, double* @d3, align 8 705 %cmp = fcmp oeq double %tmp, %tmp1 706 %cond = select i1 %cmp, i32 %f0, i32 %f1 707 ret i32 %cond 708} 709 710define i32 @f64_fcmp_olt_i32_val(i32 signext %f0, i32 signext %f1) nounwind readonly { 711entry: 712; ALL-LABEL: f64_fcmp_olt_i32_val: 713 714; 32-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp) 715; 32-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25 716; 32-DAG: lw $[[D2:[0-9]+]], %got(d2)($1) 717; 32-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]]) 718; 32-DAG: lw $[[D3:[0-9]+]], %got(d3)($1) 719; 32-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 720; 32: c.olt.d $[[TMP]], $[[TMP1]] 721; 32: movt $5, $4, $fcc0 722; 32: move $2, $5 723 724; 32R2-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp) 725; 32R2-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25 726; 32R2-DAG: lw $[[D2:[0-9]+]], %got(d2)($1) 727; 32R2-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]]) 728; 32R2-DAG: lw $[[D3:[0-9]+]], %got(d3)($1) 729; 32R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 730; 32R2: c.olt.d $[[TMP]], $[[TMP1]] 731; 32R2: movt $5, $4, $fcc0 732; 32R2: move $2, $5 733 734; 32R6-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp) 735; 32R6-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25 736; 32R6-DAG: lw $[[D2:[0-9]+]], %got(d2)($1) 737; 32R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]]) 738; 32R6-DAG: lw $[[D3:[0-9]+]], %got(d3)($1) 739; 32R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 740; 32R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]] 741; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]] 742; 32R6: andi $[[CCGPR]], $[[CCGPR]], 1 743; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]] 744; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]] 745; 32R6: or $2, $[[NE]], $[[EQ]] 746 747; 64-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val))) 748; 64-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25 749; 64-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1) 750; 64-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]]) 751; 64-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1) 752; 64-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 753; 64: c.olt.d $[[TMP]], $[[TMP1]] 754; 64: movt $5, $4, $fcc0 755; 64: move $2, $5 756 757; 64R2-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val))) 758; 64R2-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25 759; 64R2-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1) 760; 64R2-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]]) 761; 64R2-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1) 762; 64R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 763; 64R2: c.olt.d $[[TMP]], $[[TMP1]] 764; 64R2: movt $5, $4, $fcc0 765; 64R2: move $2, $5 766 767; 64R6-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val))) 768; 64R6-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25 769; 64R6-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1) 770; 64R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]]) 771; 64R6-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1) 772; 64R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 773; 64R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]] 774; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]] 775; 64R6: andi $[[CCGPR]], $[[CCGPR]], 1 776; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]] 777; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]] 778; 64R6: or $2, $[[NE]], $[[EQ]] 779 780 %tmp = load double, double* @d2, align 8 781 %tmp1 = load double, double* @d3, align 8 782 %cmp = fcmp olt double %tmp, %tmp1 783 %cond = select i1 %cmp, i32 %f0, i32 %f1 784 ret i32 %cond 785} 786 787define i32 @f64_fcmp_ogt_i32_val(i32 signext %f0, i32 signext %f1) nounwind readonly { 788entry: 789; ALL-LABEL: f64_fcmp_ogt_i32_val: 790 791; 32-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp) 792; 32-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25 793; 32-DAG: lw $[[D2:[0-9]+]], %got(d2)($1) 794; 32-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]]) 795; 32-DAG: lw $[[D3:[0-9]+]], %got(d3)($1) 796; 32-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 797; 32: c.ule.d $[[TMP]], $[[TMP1]] 798; 32: movf $5, $4, $fcc0 799; 32: move $2, $5 800 801; 32R2-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp) 802; 32R2-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25 803; 32R2-DAG: lw $[[D2:[0-9]+]], %got(d2)($1) 804; 32R2-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]]) 805; 32R2-DAG: lw $[[D3:[0-9]+]], %got(d3)($1) 806; 32R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 807; 32R2: c.ule.d $[[TMP]], $[[TMP1]] 808; 32R2: movf $5, $4, $fcc0 809; 32R2: move $2, $5 810 811; 32R6-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp) 812; 32R6-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25 813; 32R6-DAG: lw $[[D2:[0-9]+]], %got(d2)($1) 814; 32R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]]) 815; 32R6-DAG: lw $[[D3:[0-9]+]], %got(d3)($1) 816; 32R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 817; 32R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP1]], $[[TMP]] 818; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]] 819; 32R6: andi $[[CCGPR]], $[[CCGPR]], 1 820; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]] 821; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]] 822; 32R6: or $2, $[[NE]], $[[EQ]] 823 824; 64-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val))) 825; 64-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25 826; 64-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1) 827; 64-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]]) 828; 64-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1) 829; 64-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 830; 64: c.ule.d $[[TMP]], $[[TMP1]] 831; 64: movf $5, $4, $fcc0 832; 64: move $2, $5 833 834; 64R2-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val))) 835; 64R2-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25 836; 64R2-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1) 837; 64R2-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]]) 838; 64R2-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1) 839; 64R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 840; 64R2: c.ule.d $[[TMP]], $[[TMP1]] 841; 64R2: movf $5, $4, $fcc0 842; 64R2: move $2, $5 843 844; 64R6-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val))) 845; 64R6-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25 846; 64R6-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1) 847; 64R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]]) 848; 64R6-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1) 849; 64R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 850; 64R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP1]], $[[TMP]] 851; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]] 852; 64R6: andi $[[CCGPR]], $[[CCGPR]], 1 853; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]] 854; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]] 855; 64R6: or $2, $[[NE]], $[[EQ]] 856 857 %tmp = load double, double* @d2, align 8 858 %tmp1 = load double, double* @d3, align 8 859 %cmp = fcmp ogt double %tmp, %tmp1 860 %cond = select i1 %cmp, i32 %f0, i32 %f1 861 ret i32 %cond 862} 863