| /external/u-boot/drivers/pci/ |
| D | pcie_layerscape.c | 25 static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset) in dbi_readl() argument
27 return in_le32(pcie->dbi + offset); in dbi_readl()
30 static void dbi_writel(struct ls_pcie *pcie, unsigned int value, in dbi_writel() argument
33 out_le32(pcie->dbi + offset, value); in dbi_writel()
36 static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset) in ctrl_readl() argument
38 if (pcie->big_endian) in ctrl_readl()
39 return in_be32(pcie->ctrl + offset); in ctrl_readl()
41 return in_le32(pcie->ctrl + offset); in ctrl_readl()
44 static void ctrl_writel(struct ls_pcie *pcie, unsigned int value, in ctrl_writel() argument
47 if (pcie->big_endian) in ctrl_writel()
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| D | pci-aardvark.c | 150 static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg) in advk_writel() argument
152 writel(val, pcie->base + reg); in advk_writel()
155 static inline uint advk_readl(struct pcie_advk *pcie, uint reg) in advk_readl() argument
157 return readl(pcie->base + reg); in advk_readl()
191 static int pcie_advk_wait_pio(struct pcie_advk *pcie) in pcie_advk_wait_pio() argument
197 start = advk_readl(pcie, PIO_START); in pcie_advk_wait_pio()
198 isr = advk_readl(pcie, PIO_ISR); in pcie_advk_wait_pio()
208 dev_err(pcie->dev, "config read/write timed out\n"); in pcie_advk_wait_pio()
220 static int pcie_advk_check_pio_status(struct pcie_advk *pcie, in pcie_advk_check_pio_status() argument
228 reg = advk_readl(pcie, PIO_STAT); in pcie_advk_check_pio_status()
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| D | pcie_intel_fpga.c | 37 #define RP_CFG_ADDR(pcie, reg) \ argument
38 ((pcie->hip_base) + (reg) + (1 << 20))
41 #define TLP_CFGRD_DW0(pcie, bus) \ argument
42 ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGRD0 \
46 #define TLP_CFGWR_DW0(pcie, bus) \ argument
47 ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGWR0 \
51 #define TLP_CFG_DW1(pcie, tag, be) \ argument
52 (((TLP_REQ_ID(pcie->first_busno, RP_DEVFN)) << 16) | (tag << 8) | (be))
62 #define IS_ROOT_PORT(pcie, bdf) \ argument
63 ((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
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| D | pci_tegra.c | 195 struct tegra_pcie *pcie; member
240 static void afi_writel(struct tegra_pcie *pcie, unsigned long value, in afi_writel() argument
243 writel(value, pcie->afi.start + offset); in afi_writel()
246 static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset) in afi_readl() argument
248 return readl(pcie->afi.start + offset); in afi_readl()
251 static void pads_writel(struct tegra_pcie *pcie, unsigned long value, in pads_writel() argument
254 writel(value, pcie->pads.start + offset); in pads_writel()
258 static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset) in pads_readl() argument
260 return readl(pcie->pads.start + offset); in pads_readl()
283 static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf, in tegra_pcie_conf_address() argument
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| D | pci_mvebu.c | 106 static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx, in mvebu_get_port_lane() argument
114 pcie->port = port[pex_idx]; in mvebu_get_port_lane()
115 pcie->lane = lane[pex_idx]; in mvebu_get_port_lane()
141 static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx, in mvebu_get_port_lane() argument
151 pcie->port = port[pex_idx]; in mvebu_get_port_lane()
152 pcie->lane = lane[pex_idx]; in mvebu_get_port_lane()
166 static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie) in mvebu_pcie_link_up() argument
169 val = readl(pcie->base + PCIE_STAT_OFF); in mvebu_pcie_link_up()
173 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno) in mvebu_pcie_set_local_bus_nr() argument
177 stat = readl(pcie->base + PCIE_STAT_OFF); in mvebu_pcie_set_local_bus_nr()
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| D | pcie_dw_mvebu.c | 141 static void pcie_dw_prog_outbound_atu(struct pcie_dw_mvebu *pcie, int index, in pcie_dw_prog_outbound_atu() argument
146 pcie->ctrl_base + PCIE_ATU_VIEWPORT); in pcie_dw_prog_outbound_atu()
147 writel(lower_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_LOWER_BASE); in pcie_dw_prog_outbound_atu()
148 writel(upper_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_UPPER_BASE); in pcie_dw_prog_outbound_atu()
150 pcie->ctrl_base + PCIE_ATU_LIMIT); in pcie_dw_prog_outbound_atu()
152 pcie->ctrl_base + PCIE_ATU_LOWER_TARGET); in pcie_dw_prog_outbound_atu()
154 pcie->ctrl_base + PCIE_ATU_UPPER_TARGET); in pcie_dw_prog_outbound_atu()
155 writel(type, pcie->ctrl_base + PCIE_ATU_CR1); in pcie_dw_prog_outbound_atu()
156 writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2); in pcie_dw_prog_outbound_atu()
173 static uintptr_t set_cfg_address(struct pcie_dw_mvebu *pcie, in set_cfg_address() argument
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| D | pcie_layerscape_fixup.c | 25 static int ls_pcie_next_lut_index(struct ls_pcie *pcie) in ls_pcie_next_lut_index() argument
27 if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT) in ls_pcie_next_lut_index()
28 return pcie->next_lut_index++; in ls_pcie_next_lut_index()
44 static void lut_writel(struct ls_pcie *pcie, unsigned int value, in lut_writel() argument
47 if (pcie->big_endian) in lut_writel()
48 out_be32(pcie->lut + offset, value); in lut_writel()
50 out_le32(pcie->lut + offset, value); in lut_writel()
56 static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid, in ls_pcie_lut_set_mapping() argument
60 lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index)); in ls_pcie_lut_set_mapping()
61 lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index)); in ls_pcie_lut_set_mapping()
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| D | pcie_xilinx.c | 34 static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie) in pcie_xilinx_link_up() argument
36 uint32_t pscr = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_PSCR); in pcie_xilinx_link_up()
60 struct xilinx_pcie *pcie = dev_get_priv(udev); in pcie_xilinx_config_address() local
66 if ((bus > 0) && !pcie_xilinx_link_up(pcie)) in pcie_xilinx_config_address()
76 addr = pcie->cfg_base; in pcie_xilinx_config_address()
142 struct xilinx_pcie *pcie = dev_get_priv(dev); in pcie_xilinx_ofdata_to_platdata() local
154 pcie->cfg_base = map_physmem(reg_res.start, in pcie_xilinx_ofdata_to_platdata()
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| D | pcie_ecam_generic.c | 41 struct generic_ecam_pcie *pcie = dev_get_priv(bus); in pci_generic_ecam_conf_address() local
44 addr = pcie->cfg_base; in pci_generic_ecam_conf_address()
106 struct generic_ecam_pcie *pcie = dev_get_priv(dev); in pci_generic_ecam_ofdata_to_platdata() local
118 pcie->cfg_base = map_physmem(reg_res.start, in pci_generic_ecam_ofdata_to_platdata()
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| /external/u-boot/arch/arm/dts/ |
| D | tegra210-p2371-2180.dts | 24 pcie-controller@01003000 {
48 nvidia,lanes = "pcie-5", "pcie-6";
53 pcie-x1 {
54 nvidia,lanes = "pcie-0";
55 nvidia,function = "pcie-x1";
59 pcie-x4 {
60 nvidia,lanes = "pcie-1", "pcie-2",
61 "pcie-3", "pcie-4";
62 nvidia,function = "pcie-x4";
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| D | armada-xp-mv78460.dtsi | 107 pcie-controller {
108 compatible = "marvell,armada-xp-pcie";
153 pcie@1,0 {
164 marvell,pcie-port = <0>;
165 marvell,pcie-lane = <0>;
170 pcie@2,0 {
181 marvell,pcie-port = <0>;
182 marvell,pcie-lane = <1>;
187 pcie@3,0 {
198 marvell,pcie-port = <0>;
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| D | armada-xp-mv78260.dtsi | 90 pcie-controller {
91 compatible = "marvell,armada-xp-pcie";
132 pcie@1,0 {
143 marvell,pcie-port = <0>;
144 marvell,pcie-lane = <0>;
149 pcie@2,0 {
160 marvell,pcie-port = <0>;
161 marvell,pcie-lane = <1>;
166 pcie@3,0 {
177 marvell,pcie-port = <0>;
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| D | armada-385.dtsi | 79 pcie-controller {
80 compatible = "marvell,armada-370-pcie";
107 * pcie@4,0 is not available.
109 pcie@1,0 {
120 marvell,pcie-port = <0>;
121 marvell,pcie-lane = <0>;
127 pcie@2,0 {
138 marvell,pcie-port = <1>;
139 marvell,pcie-lane = <0>;
145 pcie@3,0 {
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| D | armada-xp-mv78230.dtsi | 89 pcie-controller {
90 compatible = "marvell,armada-xp-pcie";
117 pcie@1,0 {
128 marvell,pcie-port = <0>;
129 marvell,pcie-lane = <0>;
134 pcie@2,0 {
145 marvell,pcie-port = <0>;
146 marvell,pcie-lane = <1>;
151 pcie@3,0 {
162 marvell,pcie-port = <0>;
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| D | fsl-ls2080a.dtsi | 92 pcie@3400000 {
93 compatible = "fsl,ls-pcie", "snps,dw-pcie";
107 pcie@3500000 {
108 compatible = "fsl,ls-pcie", "snps,dw-pcie";
122 pcie@3600000 {
123 compatible = "fsl,ls-pcie", "snps,dw-pcie";
137 pcie@3700000 {
138 compatible = "fsl,ls-pcie", "snps,dw-pcie";
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| D | armada-380.dtsi | 74 pcie-controller {
75 compatible = "marvell,armada-370-pcie";
98 pcie@1,0 {
109 marvell,pcie-port = <0>;
110 marvell,pcie-lane = <0>;
116 pcie@2,0 {
127 marvell,pcie-port = <1>;
128 marvell,pcie-lane = <0>;
134 pcie@3,0 {
145 marvell,pcie-port = <2>;
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| D | kirkwood-98dx4122.dtsi | 4 pciec: pcie@82000000 {
5 compatible = "marvell,kirkwood-pcie";
19 pcie0: pcie@1,0 {
31 marvell,pcie-port = <0>;
32 marvell,pcie-lane = <0>;
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| D | fsl-ls1088a.dtsi | 97 pcie@3400000 {
98 compatible = "fsl,ls-pcie", "snps,dw-pcie";
113 pcie@3500000 {
114 compatible = "fsl,ls-pcie", "snps,dw-pcie";
129 pcie@3600000 {
130 compatible = "fsl,ls-pcie", "snps,dw-pcie";
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| D | kirkwood-6192.dtsi | 4 pciec: pcie@82000000 {
5 compatible = "marvell,kirkwood-pcie";
19 pcie0: pcie@1,0 {
31 marvell,pcie-port = <0>;
32 marvell,pcie-lane = <0>;
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| D | kirkwood-6281.dtsi | 4 pciec: pcie@82000000 {
5 compatible = "marvell,kirkwood-pcie";
19 pcie0: pcie@1,0 {
31 marvell,pcie-port = <0>;
32 marvell,pcie-lane = <0>;
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| D | fsl-ls1043a.dtsi | 237 pcie@3400000 {
238 compatible = "fsl,ls-pcie", "snps,dw-pcie";
252 pcie@3500000 {
253 compatible = "fsl,ls-pcie", "snps,dw-pcie";
268 pcie@3600000 {
269 compatible = "fsl,ls-pcie", "snps,dw-pcie";
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| D | fsl-ls1046a.dtsi | 238 pcie@3400000 {
239 compatible = "fsl,ls-pcie", "snps,dw-pcie";
254 pcie@3500000 {
255 compatible = "fsl,ls-pcie", "snps,dw-pcie";
271 pcie@3600000 {
272 compatible = "fsl,ls-pcie", "snps,dw-pcie";
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| D | armada-cp110-slave.dtsi | 114 "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
262 cps_pcie0: pcie@f4600000 {
263 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
288 cps_pcie1: pcie@f4620000 {
289 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
315 cps_pcie2: pcie@f4640000 {
316 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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| /external/u-boot/doc/device-tree-bindings/pci/ |
| D | armada8k-pcie.txt | 7 - compatible : should be "marvell,armada8k-pcie", "snps,dw-pcie".
8 - reg: base addresses and lengths of the pcie control and global control registers.
10 points to the pcie configuration registers as mentioned in dw-pcie dt bindings in the link below.
15 "Documentation/devicetree/bindings/pci/designware-pcie.txt"
19 - phys : phandle to phy node associated with pcie controller.
20 - phy-names : must be "pcie-phy"
25 cpm_pcie0: pcie@f2600000 {
26 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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| /external/u-boot/board/freescale/common/ |
| D | ns_access.c | 47 void set_pcie_ns_access(int pcie, u16 val) in set_pcie_ns_access() argument
49 switch (pcie) { in set_pcie_ns_access()
69 debug("The PCIE%d doesn't exist!\n", pcie); in set_pcie_ns_access()
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