Searched refs:pllcr (Results 1 – 9 of 9) sorted by relevance
| /external/u-boot/arch/m68k/cpu/mcf52x2/ |
| D | speed.c | 29 unsigned long pllcr; in get_clocks() local
36 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
38 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
43 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
48 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
49 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /external/u-boot/board/ti/ks2_evm/ |
| D | ddr3_k2g.c | 17 .pllcr = 0x000DC000ul,
57 .pllcr = 0x000DC000ul,
118 .pllcr = 0x000DC000ul,
|
| D | ddr3_cfg.c | 15 .pllcr = 0x0001C000ul,
|
| /external/u-boot/arch/arm/mach-keystone/include/mach/ |
| D | ddr3.h | 15 unsigned int pllcr; member
|
| /external/u-boot/arch/m68k/include/asm/ |
| D | immap_5307.h | 28 u8 pllcr; member
|
| /external/u-boot/arch/arm/mach-keystone/ |
| D | ddr3_spd.c | 21 debug_ddr_cfg("\npllcr 0x%08X\n", ptr->pllcr); in dump_phy_config()
304 spd_cb->phy_cfg.pllcr = (spd->freqsel & 3) << 18 | 0xE << 13; in init_ddr3param()
|
| D | ddr3.c | 32 __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET); in ddr3_init_ddrphy()
|
| /external/u-boot/arch/arm/mach-sunxi/ |
| D | dram_sun9i.c | 739 setbits_le32(&mctl_phy->pllcr, 0x3 << 19); /* PLL frequency select */ in mctl_channel_init()
741 setbits_le32(&mctl_phy->pllcr, in mctl_channel_init()
|
| /external/u-boot/arch/arm/include/asm/arch-sunxi/ |
| D | dram_sun9i.h | 97 u32 pllcr; /* 0x20 PLL control register */ member
|