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/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DCellSDKIntrinsics.td41 RRForm<0b00100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
42 "mpy $rT, $rA, $rB", IntegerMulDiv,
43 [(set (v4i32 VECREG:$rT), (int_spu_si_mpy (v8i16 VECREG:$rA),
47 RRForm<0b00110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
48 "mpyu $rT, $rA, $rB", IntegerMulDiv,
49 [(set (v4i32 VECREG:$rT), (int_spu_si_mpyu (v8i16 VECREG:$rA),
53 RI10Form<0b00101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
54 "mpyi $rT, $rA, $val", IntegerMulDiv,
55 [(set (v4i32 VECREG:$rT), (int_spu_si_mpyi (v8i16 VECREG:$rA),
59 RI10Form<0b10101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
[all …]
DSPUInstrInfo.td477 // fsmb: Form select mask for bytes. N.B. Input operand, $rA, is 16-bits
479 RRForm_1<0b01101101100, OOL, IOL, "fsmb\t$rT, $rA", SelectOp,
483 FSMBInst<(outs VECREG:$rT), (ins rclass:$rA),
484 [(set (vectype VECREG:$rT), (SPUselmask rclass:$rA))]>;
487 FSMBInst<(outs VECREG:$rT), (ins VECREG:$rA),
489 (SPUselmask (vectype VECREG:$rA)))]>;
498 // fsmh: Form select mask for halfwords. N.B., Input operand, $rA, is
502 RRForm_1<0b10101101100, OOL, IOL, "fsmh\t$rT, $rA", SelectOp,
506 FSMHInst<(outs VECREG:$rT), (ins rclass:$rA),
507 [(set (vectype VECREG:$rT), (SPUselmask rclass:$rA))]>;
[all …]
DSPU64InstrInfo.td33 SELBInst<(outs R64C:$rT), (ins R64C:$rA, R64C:$rB, VECREG:$rC),
45 Pat<(select (i32 (cond R64C:$rA, R64C:$rB)), R64C:$rTrue, R64C:$rFalse),
50 Pat<(cond R64C:$rA, R64C:$rB),
57 CodeFrag<(CGTIv4i32 (GBv4i32 (CEQv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG),
62 CodeFrag<(CEQIv4i32 (GBv4i32 (CEQv4i32 VECREG:$rA, VECREG:$rB)), 0xf)>;
82 def : Pat<(seteq R64C:$rA, R64C:$rB), I64EQr64.Fragment>;
83 def : Pat<(seteq (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)), I64EQv2i64.Fragment>;
94 CodeFrag<(CLGTv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG),
98 CodeFrag<(CEQv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG),
107 CodeFrag<(CLGTv4i32 VECREG:$rA, VECREG:$rB)>;
[all …]
DSPUMathInstr.td17 def : Pat<(mul (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)),
20 (SELBv4i32 (MPYv8i16 VECREG:$rA, VECREG:$rB),
21 (SHLHIv8i16 (MPYv8i16 (ROTMAHIv8i16 VECREG:$rA, 8),
26 (SELBv4i32 (MPYv8i16 (ROTMAIv4i32_i32 VECREG:$rA, 16),
28 (SHLHIv8i16 (MPYv8i16 (ROTMAIv4i32_i32 VECREG:$rA, 8),
36 def : Pat<(mul (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)),
37 (SELBv8i16 (MPYv8i16 VECREG:$rA, VECREG:$rB),
38 (SHLIv4i32 (MPYHHv8i16 VECREG:$rA, VECREG:$rB), 16),
46 Pat<(mul (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)),
48 (v4i32 (Av4i32 (v4i32 (MPYHv4i32 VECREG:$rA, VECREG:$rB)),
[all …]
DSPUInstrFormats.td259 RI10Form<opcode, (outs VECREG:$rT), (ins s10imm:$val, VECREG:$rA),
260 !strconcat(opc, " $rT, $rA, $val"), itin,
261 [(set (v8i16 VECREG:$rT), (IntID (v8i16 VECREG:$rA),
266 RI10Form<opcode, (outs VECREG:$rT), (ins s10imm:$val, VECREG:$rA),
267 !strconcat(opc, " $rT, $rA, $val"), itin,
268 [(set (v4i32 VECREG:$rT), (IntID (v4i32 VECREG:$rA),
274 RRForm<opcode, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
275 !strconcat(opc, " $rT, $rA, $rB"), itin,
276 [(set (v8i16 VECREG:$rT), (IntID (v8i16 VECREG:$rA),
282 RRForm<opcode, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
[all …]
DSPU128InstrInfo.td40 def : Pat<(shl GPRC:$rA, R32C:$rB),
41 (SHLQBYBIr128 (SHLQBIr128 GPRC:$rA, R32C:$rB), R32C:$rB)>;
/external/swiftshader/third_party/LLVM/test/CodeGen/CellSPU/
Dselect_bits.ll11 ; (or (and rC, rB), (and (not rC), rA))
12 define <2 x i64> @selectbits_v2i64_01(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
15 %B = and <2 x i64> %A, %rA
20 ; (or (and rB, rC), (and (not rC), rA))
21 define <2 x i64> @selectbits_v2i64_02(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
24 %B = and <2 x i64> %A, %rA
29 ; (or (and (not rC), rA), (and rB, rC))
30 define <2 x i64> @selectbits_v2i64_03(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
32 %B = and <2 x i64> %A, %rA
38 ; (or (and (not rC), rA), (and rC, rB))
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCInstr64Bit.td264 def OR4To8 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB),
265 "or $rA, $rS, $rB", IntGeneral,
267 def OR8To4 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB),
268 "or $rA, $rS, $rB", IntGeneral,
279 def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
280 "nand $rA, $rS, $rB", IntGeneral,
281 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>;
282 def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
283 "and $rA, $rS, $rB", IntGeneral,
284 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>;
[all …]
DPPCInstrInfo.td819 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
820 "stwux $rS, $rA, $rB", LdStGeneral,
853 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
854 "addi $rD, $rA, $imm", IntGeneral,
855 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
857 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
858 "addic $rD, $rA, $imm", IntGeneral,
859 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
861 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
862 "addic. $rD, $rA, $imm", IntGeneral,
[all …]
DPPCInstrAltivec.td196 (ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
197 "dst $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>;
199 (ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
200 "dstt $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>;
202 (ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
203 "dstst $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>;
205 (ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
206 "dststt $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>;
209 (ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
210 "dst $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td256 def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC),
257 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64,
266 def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC),
267 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64,
437 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
438 "nand", "$rA, $rS, $rB", IIC_IntSimple,
439 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
440 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
441 "and", "$rA, $rS, $rB", IIC_IntSimple,
442 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
[all …]
DPPCInstrInfo.td1800 def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC),
1801 "lwat $rD, $rA, $FC", IIC_LdStLoad>,
1819 def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC),
1820 "stwat $rS, $rA, $FC", IIC_LdStStore>,
1826 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1827 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1828 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1829 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1830 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1831 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
[all …]
DREADME_P9.txt23 (set i64:$rD, (int_ppc_altivec_vextublx i64:$rA, v16i8:$vB))
24 (set i64:$rD, (int_ppc_altivec_vextuhlx i64:$rA, v8i16:$vB))
25 (set i64:$rD, (int_ppc_altivec_vextuwlx i64:$rA, v4i32:$vB))
28 (set i64:$rD, (int_ppc_altivec_vextubrx i64:$rA, v16i8:$vB))
29 (set i64:$rD, (int_ppc_altivec_vextuhrx i64:$rA, v8i16:$vB))
30 (set i64:$rD, (int_ppc_altivec_vextuwrx i64:$rA, v4i32:$vB))
94 (set v4i32:$rT, (ineg v4i32:$rA)) // vnegw
95 (set v2i64:$rT, (ineg v2i64:$rA)) // vnegd
386 // Note: rA and rB are the unsigned integer value.
387 (set f128:$XT, (int_ppc_vsx_xsiexpdp i64:$rA, i64:$rB))
[all …]
DPPCInstrAltivec.td358 def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
359 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
360 [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>,
363 def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
364 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
365 [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>,
368 def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
369 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
370 [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>,
373 def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td249 def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC),
250 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64,
259 def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC),
260 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64,
430 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
431 "nand", "$rA, $rS, $rB", IIC_IntSimple,
432 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
433 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
434 "and", "$rA, $rS, $rB", IIC_IntSimple,
435 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
[all …]
DPPCInstrInfo.td1600 def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC),
1601 "lwat $rD, $rA, $FC", IIC_LdStLoad>,
1619 def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC),
1620 "stwat $rS, $rA, $FC", IIC_LdStStore>,
1626 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1627 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1628 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1629 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1630 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1631 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
[all …]
DREADME_P9.txt23 (set i64:$rD, (int_ppc_altivec_vextublx i64:$rA, v16i8:$vB))
24 (set i64:$rD, (int_ppc_altivec_vextuhlx i64:$rA, v8i16:$vB))
25 (set i64:$rD, (int_ppc_altivec_vextuwlx i64:$rA, v4i32:$vB))
28 (set i64:$rD, (int_ppc_altivec_vextubrx i64:$rA, v16i8:$vB))
29 (set i64:$rD, (int_ppc_altivec_vextuhrx i64:$rA, v8i16:$vB))
30 (set i64:$rD, (int_ppc_altivec_vextuwrx i64:$rA, v4i32:$vB))
94 (set v4i32:$rT, (ineg v4i32:$rA)) // vnegw
95 (set v2i64:$rT, (ineg v2i64:$rA)) // vnegd
386 // Note: rA and rB are the unsigned integer value.
387 (set f128:$XT, (int_ppc_vsx_xsiexpdp i64:$rA, i64:$rB))
[all …]
DPPCInstrAltivec.td357 def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
358 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
359 [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>,
362 def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
363 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
364 [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>,
367 def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
368 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
369 [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>,
372 def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
[all …]
DPPCInstrVSX.td1243 def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT),
1244 "mfvsrd $rA, $XT", IIC_VecGeneral,
1245 [(set i64:$rA, (PPCmfvsr f64:$XT))]>,
1247 def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
1248 "mfvsrwz $rA, $XT", IIC_VecGeneral,
1249 [(set i32:$rA, (PPCmfvsr f64:$XT))]>;
1250 def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$rA),
1251 "mtvsrd $XT, $rA", IIC_VecGeneral,
1252 [(set f64:$XT, (PPCmtvsra i64:$rA))]>,
1254 def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$rA),
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Nios2/
DNios2InstrInfo.td46 (ins CPURegs:$rA, immOp:$imm),
47 !strconcat(mnemonic, "\t$rB, $rA, $imm"),
49 (opNode CPURegs:$rA, immType:$imm))],
57 (ins CPURegs:$rA, CPURegs:$rB),
58 !strconcat(mnemonic, "\t$rC, $rA, $rB"),
59 [(set CPURegs:$rC, (opNode CPURegs:$rA, CPURegs:$rB))],
101 defm RET : Return<0x05, (outs), (ins CPURegs:$rA), "ret">;
DNios2InstrFormats.td138 bits<5> rA;
144 let Inst{31-27} = rA;
157 bits<5> rA;
164 let Inst{31-27} = rA;
192 bits<5> rA;
201 let Inst{10-6} = rA;
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir_util.cpp180 for (Range *rA = this->head; rA; rA = rA->next) in overlaps()
182 if (rB->bgn < rA->end && in overlaps()
183 rB->end > rA->bgn) in overlaps()
/external/neven/Embedded/common/src/b_BasicEm/
DMath.c1048 …ltiplyFlt16( const int16 *x1A, int16 row1A, int16 col1A, const int16 *x2A, int16 col2A, int16 *rA ) in bbs_matMultiplyFlt16() argument
1071 *rA++ = ( sumL + ( 1 << 14 ) ) >> 15; /* round result to 1.15 */ in bbs_matMultiplyFlt16()
1075 else mmul( ( int16* ) x1A, row1A, col1A, ( int16* ) x2A, col1A, col2A, rA ); in bbs_matMultiplyFlt16()
1102 *rA++ = ( sumL + ( 1 << 14 ) ) >> 15; /* round result to 1.15 */ in bbs_matMultiplyFlt16()
1123 *rA++ = ( sumL + ( 1 << 14 ) ) >> 15; /* round result to 1.15 */ in bbs_matMultiplyFlt16()
1132 const int16 *x2A, int16 col2A, int16 *rA ) in bbs_matMultiplyTranspFlt16() argument
1156 *rA++ = ( sumL + ( 1 << 14 ) ) >> 15; /* round result to 1.15 */ in bbs_matMultiplyTranspFlt16()
1167 uint16 bbs_matTrans( int16 *xA, int16 rowA, int16 colA, int16 *rA ) in bbs_matTrans() argument
1177 *rA++ = *sL; in bbs_matTrans()
DMath.h181 const int16 *x2A, int16 col2A, int16 *rA );
185 const int16 *x2A, int16 row2A, int16 *rA );
/external/capstone/arch/PowerPC/
DPPCGenAsmWriter.inc5950 // (CMPD CR0, g8rc:$rA, g8rc:$rB)
5960 // (CMPDI CR0, g8rc:$rA, s16imm64:$imm)
5972 // (CMPLD CR0, g8rc:$rA, g8rc:$rB)
5982 // (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)
5994 // (CMPLW CR0, gprc:$rA, gprc:$rB)
6004 // (CMPLWI CR0, gprc:$rA, u16imm:$imm)
6016 // (CMPW CR0, gprc:$rA, gprc:$rB)
6026 // (CMPWI CR0, gprc:$rA, s16imm:$imm)
6518 // (MTCRF8 255, g8rc:$rA)
6944 // (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)
[all …]

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