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1//===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Altivec extension to the PowerPC instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14// *********************************** NOTE ***********************************
15// ** For POWER8 Little Endian, the VSX swap optimization relies on knowing  **
16// ** which VMX and VSX instructions are lane-sensitive and which are not.   **
17// ** A lane-sensitive instruction relies, implicitly or explicitly, on      **
18// ** whether lanes are numbered from left to right.  An instruction like    **
19// ** VADDFP is not lane-sensitive, because each lane of the result vector   **
20// ** relies only on the corresponding lane of the source vectors.  However, **
21// ** an instruction like VMULESB is lane-sensitive, because "even" and      **
22// ** "odd" lanes are different for big-endian and little-endian numbering.  **
23// **                                                                        **
24// ** When adding new VMX and VSX instructions, please consider whether they **
25// ** are lane-sensitive.  If so, they must be added to a switch statement   **
26// ** in PPCVSXSwapRemoval::gatherVectorInstructions().                      **
27// ****************************************************************************
28
29//===----------------------------------------------------------------------===//
30// Altivec transformation functions and pattern fragments.
31//
32
33// Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be
34// of that type.
35def vnot_ppc : PatFrag<(ops node:$in),
36                       (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>;
37
38def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
39                              (vector_shuffle node:$lhs, node:$rhs), [{
40  return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG);
41}]>;
42def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
43                              (vector_shuffle node:$lhs, node:$rhs), [{
44  return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG);
45}]>;
46def vpkudum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
47                              (vector_shuffle node:$lhs, node:$rhs), [{
48  return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG);
49}]>;
50def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
51                                    (vector_shuffle node:$lhs, node:$rhs), [{
52  return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);
53}]>;
54def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
55                                    (vector_shuffle node:$lhs, node:$rhs), [{
56  return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);
57}]>;
58def vpkudum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
59                                    (vector_shuffle node:$lhs, node:$rhs), [{
60  return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);
61}]>;
62
63// These fragments are provided for little-endian, where the inputs must be
64// swapped for correct semantics.
65def vpkuhum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
66                                      (vector_shuffle node:$lhs, node:$rhs), [{
67  return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG);
68}]>;
69def vpkuwum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
70                                      (vector_shuffle node:$lhs, node:$rhs), [{
71  return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG);
72}]>;
73def vpkudum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
74                                      (vector_shuffle node:$lhs, node:$rhs), [{
75  return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG);
76}]>;
77
78def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
79                             (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
80  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG);
81}]>;
82def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
83                             (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
84  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG);
85}]>;
86def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
87                             (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
88  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG);
89}]>;
90def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
91                             (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
92  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG);
93}]>;
94def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
95                             (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
96  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG);
97}]>;
98def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
99                             (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
100  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG);
101}]>;
102
103
104def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
105                               (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
106  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG);
107}]>;
108def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
109                                   (vector_shuffle node:$lhs, node:$rhs), [{
110  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG);
111}]>;
112def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
113                                   (vector_shuffle node:$lhs, node:$rhs), [{
114  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG);
115}]>;
116def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
117                                   (vector_shuffle node:$lhs, node:$rhs), [{
118  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG);
119}]>;
120def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
121                                   (vector_shuffle node:$lhs, node:$rhs), [{
122  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG);
123}]>;
124def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
125                                   (vector_shuffle node:$lhs, node:$rhs), [{
126  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG);
127}]>;
128
129
130// These fragments are provided for little-endian, where the inputs must be
131// swapped for correct semantics.
132def vmrglb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
133                               (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
134  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG);
135}]>;
136def vmrglh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
137                                   (vector_shuffle node:$lhs, node:$rhs), [{
138  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG);
139}]>;
140def vmrglw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
141                                   (vector_shuffle node:$lhs, node:$rhs), [{
142  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG);
143}]>;
144def vmrghb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
145                                   (vector_shuffle node:$lhs, node:$rhs), [{
146  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG);
147}]>;
148def vmrghh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
149                                   (vector_shuffle node:$lhs, node:$rhs), [{
150  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG);
151}]>;
152def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
153                                   (vector_shuffle node:$lhs, node:$rhs), [{
154  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG);
155}]>;
156
157
158def vmrgew_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
159                             (vector_shuffle node:$lhs, node:$rhs), [{
160  return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 0, *CurDAG);
161}]>;
162def vmrgow_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
163                             (vector_shuffle node:$lhs, node:$rhs), [{
164  return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 0, *CurDAG);
165}]>;
166def vmrgew_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
167                                   (vector_shuffle node:$lhs, node:$rhs), [{
168  return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 1, *CurDAG);
169}]>;
170def vmrgow_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
171                                   (vector_shuffle node:$lhs, node:$rhs), [{
172  return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 1, *CurDAG);
173}]>;
174def vmrgew_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
175                                     (vector_shuffle node:$lhs, node:$rhs), [{
176  return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 2, *CurDAG);
177}]>;
178def vmrgow_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
179                                     (vector_shuffle node:$lhs, node:$rhs), [{
180  return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 2, *CurDAG);
181}]>;
182
183
184
185def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{
186  return getI32Imm(PPC::isVSLDOIShuffleMask(N, 0, *CurDAG), SDLoc(N));
187}]>;
188def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
189                             (vector_shuffle node:$lhs, node:$rhs), [{
190  return PPC::isVSLDOIShuffleMask(N, 0, *CurDAG) != -1;
191}], VSLDOI_get_imm>;
192
193
194/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into
195/// vector_shuffle(X,undef,mask) by the dag combiner.
196def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{
197  return getI32Imm(PPC::isVSLDOIShuffleMask(N, 1, *CurDAG), SDLoc(N));
198}]>;
199def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
200                                   (vector_shuffle node:$lhs, node:$rhs), [{
201  return PPC::isVSLDOIShuffleMask(N, 1, *CurDAG) != -1;
202}], VSLDOI_unary_get_imm>;
203
204
205/// VSLDOI_swapped* - These fragments are provided for little-endian, where
206/// the inputs must be swapped for correct semantics.
207def VSLDOI_swapped_get_imm : SDNodeXForm<vector_shuffle, [{
208  return getI32Imm(PPC::isVSLDOIShuffleMask(N, 2, *CurDAG), SDLoc(N));
209}]>;
210def vsldoi_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
211                                     (vector_shuffle node:$lhs, node:$rhs), [{
212  return PPC::isVSLDOIShuffleMask(N, 2, *CurDAG) != -1;
213}], VSLDOI_get_imm>;
214
215
216// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
217def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{
218  return getI32Imm(PPC::getVSPLTImmediate(N, 1, *CurDAG), SDLoc(N));
219}]>;
220def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
221                             (vector_shuffle node:$lhs, node:$rhs), [{
222  return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1);
223}], VSPLTB_get_imm>;
224def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{
225  return getI32Imm(PPC::getVSPLTImmediate(N, 2, *CurDAG), SDLoc(N));
226}]>;
227def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
228                             (vector_shuffle node:$lhs, node:$rhs), [{
229  return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2);
230}], VSPLTH_get_imm>;
231def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{
232  return getI32Imm(PPC::getVSPLTImmediate(N, 4, *CurDAG), SDLoc(N));
233}]>;
234def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
235                             (vector_shuffle node:$lhs, node:$rhs), [{
236  return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4);
237}], VSPLTW_get_imm>;
238
239
240// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
241def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
242  return PPC::get_VSPLTI_elt(N, 1, *CurDAG);
243}]>;
244def vecspltisb : PatLeaf<(build_vector), [{
245  return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0;
246}], VSPLTISB_get_imm>;
247
248// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
249def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
250  return PPC::get_VSPLTI_elt(N, 2, *CurDAG);
251}]>;
252def vecspltish : PatLeaf<(build_vector), [{
253  return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0;
254}], VSPLTISH_get_imm>;
255
256// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
257def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
258  return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
259}]>;
260def vecspltisw : PatLeaf<(build_vector), [{
261  return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0;
262}], VSPLTISW_get_imm>;
263
264//===----------------------------------------------------------------------===//
265// Helpers for defining instructions that directly correspond to intrinsics.
266
267// VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type.
268class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty>
269  : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
270              !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
271                       [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>;
272
273// VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the
274// inputs doesn't match the type of the output.
275class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
276                   ValueType InTy>
277  : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
278              !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
279                       [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>;
280
281// VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two
282// input types and an output type.
283class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
284                   ValueType In1Ty, ValueType In2Ty>
285  : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
286              !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
287                       [(set OutTy:$vD,
288                         (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>;
289
290// VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type.
291class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
292  : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
293             !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
294             [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>;
295
296// VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the
297// inputs doesn't match the type of the output.
298class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
299                  ValueType InTy>
300  : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
301             !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
302             [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>;
303
304// VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two
305// input types and an output type.
306class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
307                  ValueType In1Ty, ValueType In2Ty>
308  : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
309             !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
310             [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>;
311
312// VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type.
313class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID>
314  : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
315             !strconcat(opc, " $vD, $vB"), IIC_VecFP,
316             [(set v4f32:$vD, (IntID v4f32:$vB))]>;
317
318// VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the
319// inputs doesn't match the type of the output.
320class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
321                  ValueType InTy>
322  : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
323             !strconcat(opc, " $vD, $vB"), IIC_VecFP,
324             [(set OutTy:$vD, (IntID InTy:$vB))]>;
325
326class VXBX_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
327  : VXForm_BX<xo, (outs vrrc:$vD), (ins vrrc:$vA),
328             !strconcat(opc, " $vD, $vA"), IIC_VecFP,
329             [(set Ty:$vD, (IntID Ty:$vA))]>;
330
331class VXCR_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
332  : VXForm_CR<xo, (outs vrrc:$vD), (ins vrrc:$vA, u1imm:$ST, u4imm:$SIX),
333              !strconcat(opc, " $vD, $vA, $ST, $SIX"), IIC_VecFP,
334              [(set Ty:$vD, (IntID Ty:$vA, imm:$ST, imm:$SIX))]>;
335
336//===----------------------------------------------------------------------===//
337// Instruction Definitions.
338
339def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">;
340let Predicates = [HasAltivec] in {
341
342def DSS      : DSS_Form<0, 822, (outs), (ins u5imm:$STRM),
343                        "dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>,
344                        Deprecated<DeprecatedDST> {
345  let A = 0;
346  let B = 0;
347}
348
349def DSSALL   : DSS_Form<1, 822, (outs), (ins),
350                        "dssall", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dssall)]>,
351                        Deprecated<DeprecatedDST> {
352  let STRM = 0;
353  let A = 0;
354  let B = 0;
355}
356
357def DST      : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
358                        "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
359                        [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>,
360                        Deprecated<DeprecatedDST>;
361
362def DSTT     : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
363                        "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
364                        [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>,
365                        Deprecated<DeprecatedDST>;
366
367def DSTST    : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
368                        "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
369                        [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>,
370                        Deprecated<DeprecatedDST>;
371
372def DSTSTT   : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
373                        "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
374                        [(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM)]>,
375                        Deprecated<DeprecatedDST>;
376
377let isCodeGenOnly = 1 in {
378  // The very same instructions as above, but formally matching 64bit registers.
379  def DST64    : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
380                          "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
381                          [(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM)]>,
382                          Deprecated<DeprecatedDST>;
383
384  def DSTT64   : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
385                          "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
386                          [(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM)]>,
387                          Deprecated<DeprecatedDST>;
388
389  def DSTST64  : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
390                          "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
391                          [(int_ppc_altivec_dstst i64:$rA, i32:$rB,
392                                                  imm:$STRM)]>,
393                          Deprecated<DeprecatedDST>;
394
395  def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
396                          "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
397                          [(int_ppc_altivec_dststt i64:$rA, i32:$rB,
398                                                   imm:$STRM)]>,
399                          Deprecated<DeprecatedDST>;
400}
401
402def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins),
403                      "mfvscr $vD", IIC_LdStStore,
404                      [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>;
405def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB),
406                      "mtvscr $vB", IIC_LdStLoad,
407                      [(int_ppc_altivec_mtvscr v4i32:$vB)]>;
408
409let PPC970_Unit = 2 in {  // Loads.
410def LVEBX: XForm_1<31,   7, (outs vrrc:$vD), (ins memrr:$src),
411                   "lvebx $vD, $src", IIC_LdStLoad,
412                   [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
413def LVEHX: XForm_1<31,  39, (outs vrrc:$vD), (ins memrr:$src),
414                   "lvehx $vD, $src", IIC_LdStLoad,
415                   [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
416def LVEWX: XForm_1<31,  71, (outs vrrc:$vD), (ins memrr:$src),
417                   "lvewx $vD, $src", IIC_LdStLoad,
418                   [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
419def LVX  : XForm_1<31, 103, (outs vrrc:$vD), (ins memrr:$src),
420                   "lvx $vD, $src", IIC_LdStLoad,
421                   [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
422def LVXL : XForm_1<31, 359, (outs vrrc:$vD), (ins memrr:$src),
423                   "lvxl $vD, $src", IIC_LdStLoad,
424                   [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
425}
426
427def LVSL : XForm_1<31,   6, (outs vrrc:$vD), (ins memrr:$src),
428                   "lvsl $vD, $src", IIC_LdStLoad,
429                   [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
430                   PPC970_Unit_LSU;
431def LVSR : XForm_1<31,  38, (outs vrrc:$vD), (ins memrr:$src),
432                   "lvsr $vD, $src", IIC_LdStLoad,
433                   [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
434                   PPC970_Unit_LSU;
435
436let PPC970_Unit = 2 in {   // Stores.
437def STVEBX: XForm_8<31, 135, (outs), (ins vrrc:$rS, memrr:$dst),
438                   "stvebx $rS, $dst", IIC_LdStStore,
439                   [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>;
440def STVEHX: XForm_8<31, 167, (outs), (ins vrrc:$rS, memrr:$dst),
441                   "stvehx $rS, $dst", IIC_LdStStore,
442                   [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>;
443def STVEWX: XForm_8<31, 199, (outs), (ins vrrc:$rS, memrr:$dst),
444                   "stvewx $rS, $dst", IIC_LdStStore,
445                   [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>;
446def STVX  : XForm_8<31, 231, (outs), (ins vrrc:$rS, memrr:$dst),
447                   "stvx $rS, $dst", IIC_LdStStore,
448                   [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>;
449def STVXL : XForm_8<31, 487, (outs), (ins vrrc:$rS, memrr:$dst),
450                   "stvxl $rS, $dst", IIC_LdStStore,
451                   [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>;
452}
453
454let PPC970_Unit = 5 in {  // VALU Operations.
455// VA-Form instructions.  3-input AltiVec ops.
456let isCommutable = 1 in {
457def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
458                       "vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP,
459                       [(set v4f32:$vD,
460                        (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>;
461
462// FIXME: The fma+fneg pattern won't match because fneg is not legal.
463def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
464                       "vnmsubfp $vD, $vA, $vC, $vB", IIC_VecFP,
465                       [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC,
466                                                  (fneg v4f32:$vB))))]>;
467
468def VMHADDSHS  : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>;
469def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs,
470                             v8i16>;
471def VMLADDUHM  : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>;
472} // isCommutable
473
474def VPERM      : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm,
475                              v4i32, v4i32, v16i8>;
476def VSEL       : VA1a_Int_Ty<42, "vsel",  int_ppc_altivec_vsel, v4i32>;
477
478// Shuffles.
479def VSLDOI  : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u5imm:$SH),
480                       "vsldoi $vD, $vA, $vB, $SH", IIC_VecFP,
481                       [(set v16i8:$vD,
482                         (vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB))]>;
483
484// VX-Form instructions.  AltiVec arithmetic ops.
485let isCommutable = 1 in {
486def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
487                      "vaddfp $vD, $vA, $vB", IIC_VecFP,
488                      [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>;
489
490def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
491                      "vaddubm $vD, $vA, $vB", IIC_VecGeneral,
492                      [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>;
493def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
494                      "vadduhm $vD, $vA, $vB", IIC_VecGeneral,
495                      [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>;
496def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
497                      "vadduwm $vD, $vA, $vB", IIC_VecGeneral,
498                      [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>;
499
500def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>;
501def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>;
502def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>;
503def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>;
504def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>;
505def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>;
506def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>;
507} // isCommutable
508
509let isCommutable = 1 in
510def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
511                    "vand $vD, $vA, $vB", IIC_VecFP,
512                    [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>;
513def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
514                     "vandc $vD, $vA, $vB", IIC_VecFP,
515                     [(set v4i32:$vD, (and v4i32:$vA,
516                                           (vnot_ppc v4i32:$vB)))]>;
517
518def VCFSX  : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
519                      "vcfsx $vD, $vB, $UIMM", IIC_VecFP,
520                      [(set v4f32:$vD,
521                             (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>;
522def VCFUX  : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
523                      "vcfux $vD, $vB, $UIMM", IIC_VecFP,
524                      [(set v4f32:$vD,
525                             (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>;
526def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
527                      "vctsxs $vD, $vB, $UIMM", IIC_VecFP,
528                      [(set v4i32:$vD,
529                             (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>;
530def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
531                      "vctuxs $vD, $vB, $UIMM", IIC_VecFP,
532                      [(set v4i32:$vD,
533                             (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>;
534
535// Defines with the UIM field set to 0 for floating-point
536// to integer (fp_to_sint/fp_to_uint) conversions and integer
537// to floating-point (sint_to_fp/uint_to_fp) conversions.
538let isCodeGenOnly = 1, VA = 0 in {
539def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB),
540                       "vcfsx $vD, $vB, 0", IIC_VecFP,
541                       [(set v4f32:$vD,
542                             (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>;
543def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB),
544                        "vctuxs $vD, $vB, 0", IIC_VecFP,
545                        [(set v4i32:$vD,
546                               (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>;
547def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB),
548                       "vcfux $vD, $vB, 0", IIC_VecFP,
549                       [(set v4f32:$vD,
550                               (int_ppc_altivec_vcfux v4i32:$vB, 0))]>;
551def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB),
552                      "vctsxs $vD, $vB, 0", IIC_VecFP,
553                      [(set v4i32:$vD,
554                             (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>;
555}
556def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>;
557def VLOGEFP  : VX2_Int_SP<458, "vlogefp",  int_ppc_altivec_vlogefp>;
558
559let isCommutable = 1 in {
560def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>;
561def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>;
562def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>;
563def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>;
564def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>;
565def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>;
566
567def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>;
568def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>;
569def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>;
570def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>;
571def VMAXUB : VX1_Int_Ty<   2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>;
572def VMAXUH : VX1_Int_Ty<  66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>;
573def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>;
574def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>;
575def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>;
576def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>;
577def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>;
578def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>;
579def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>;
580def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>;
581} // isCommutable
582
583def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
584                      "vmrghb $vD, $vA, $vB", IIC_VecFP,
585                      [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>;
586def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
587                      "vmrghh $vD, $vA, $vB", IIC_VecFP,
588                      [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>;
589def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
590                      "vmrghw $vD, $vA, $vB", IIC_VecFP,
591                      [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>;
592def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
593                      "vmrglb $vD, $vA, $vB", IIC_VecFP,
594                      [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>;
595def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
596                      "vmrglh $vD, $vA, $vB", IIC_VecFP,
597                      [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>;
598def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
599                      "vmrglw $vD, $vA, $vB", IIC_VecFP,
600                      [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>;
601
602def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm,
603                            v4i32, v16i8, v4i32>;
604def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm,
605                            v4i32, v8i16, v4i32>;
606def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs,
607                            v4i32, v8i16, v4i32>;
608def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm,
609                            v4i32, v16i8, v4i32>;
610def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm,
611                            v4i32, v8i16, v4i32>;
612def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs,
613                            v4i32, v8i16, v4i32>;
614
615let isCommutable = 1 in {
616def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb,
617                          v8i16, v16i8>;
618def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh,
619                          v4i32, v8i16>;
620def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub,
621                          v8i16, v16i8>;
622def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh,
623                          v4i32, v8i16>;
624def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb,
625                          v8i16, v16i8>;
626def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh,
627                          v4i32, v8i16>;
628def VMULOUB : VX1_Int_Ty2<  8, "vmuloub", int_ppc_altivec_vmuloub,
629                          v8i16, v16i8>;
630def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh,
631                          v4i32, v8i16>;
632} // isCommutable
633
634def VREFP     : VX2_Int_SP<266, "vrefp",     int_ppc_altivec_vrefp>;
635def VRFIM     : VX2_Int_SP<714, "vrfim",     int_ppc_altivec_vrfim>;
636def VRFIN     : VX2_Int_SP<522, "vrfin",     int_ppc_altivec_vrfin>;
637def VRFIP     : VX2_Int_SP<650, "vrfip",     int_ppc_altivec_vrfip>;
638def VRFIZ     : VX2_Int_SP<586, "vrfiz",     int_ppc_altivec_vrfiz>;
639def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
640
641def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>;
642
643def VSUBFP  : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
644                      "vsubfp $vD, $vA, $vB", IIC_VecGeneral,
645                      [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>;
646def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
647                      "vsububm $vD, $vA, $vB", IIC_VecGeneral,
648                      [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>;
649def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
650                      "vsubuhm $vD, $vA, $vB", IIC_VecGeneral,
651                      [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>;
652def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
653                      "vsubuwm $vD, $vA, $vB", IIC_VecGeneral,
654                      [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>;
655
656def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>;
657def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>;
658def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>;
659def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>;
660def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>;
661def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>;
662
663def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>;
664def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>;
665
666def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs,
667                          v4i32, v16i8, v4i32>;
668def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs,
669                          v4i32, v8i16, v4i32>;
670def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs,
671                          v4i32, v16i8, v4i32>;
672
673def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
674                    "vnor $vD, $vA, $vB", IIC_VecFP,
675                    [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA,
676                                                   v4i32:$vB)))]>;
677let isCommutable = 1 in {
678def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
679                      "vor $vD, $vA, $vB", IIC_VecFP,
680                      [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>;
681def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
682                      "vxor $vD, $vA, $vB", IIC_VecFP,
683                      [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>;
684} // isCommutable
685
686def VRLB   : VX1_Int_Ty<   4, "vrlb", int_ppc_altivec_vrlb, v16i8>;
687def VRLH   : VX1_Int_Ty<  68, "vrlh", int_ppc_altivec_vrlh, v8i16>;
688def VRLW   : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>;
689
690def VSL    : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl,  v4i32 >;
691def VSLO   : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>;
692
693def VSLB   : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>;
694def VSLH   : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>;
695def VSLW   : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>;
696
697def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
698                      "vspltb $vD, $vB, $UIMM", IIC_VecPerm,
699                      [(set v16i8:$vD,
700                        (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>;
701def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
702                      "vsplth $vD, $vB, $UIMM", IIC_VecPerm,
703                      [(set v16i8:$vD,
704                        (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>;
705def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
706                      "vspltw $vD, $vB, $UIMM", IIC_VecPerm,
707                      [(set v16i8:$vD,
708                        (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>;
709
710def VSR    : VX1_Int_Ty< 708, "vsr"  , int_ppc_altivec_vsr,  v4i32>;
711def VSRO   : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>;
712
713def VSRAB  : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>;
714def VSRAH  : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>;
715def VSRAW  : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>;
716def VSRB   : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>;
717def VSRH   : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>;
718def VSRW   : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>;
719
720
721def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM),
722                       "vspltisb $vD, $SIMM", IIC_VecPerm,
723                       [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>;
724def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM),
725                       "vspltish $vD, $SIMM", IIC_VecPerm,
726                       [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>;
727def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM),
728                       "vspltisw $vD, $SIMM", IIC_VecPerm,
729                       [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>;
730
731// Vector Pack.
732def VPKPX   : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx,
733                          v8i16, v4i32>;
734def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss,
735                          v16i8, v8i16>;
736def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus,
737                          v16i8, v8i16>;
738def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss,
739                          v8i16, v4i32>;
740def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus,
741                          v8i16, v4i32>;
742def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
743                       "vpkuhum $vD, $vA, $vB", IIC_VecFP,
744                       [(set v16i8:$vD,
745                         (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>;
746def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus,
747                          v16i8, v8i16>;
748def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
749                       "vpkuwum $vD, $vA, $vB", IIC_VecFP,
750                       [(set v16i8:$vD,
751                         (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>;
752def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus,
753                          v8i16, v4i32>;
754
755// Vector Unpack.
756def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx,
757                          v4i32, v8i16>;
758def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb,
759                          v8i16, v16i8>;
760def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh,
761                          v4i32, v8i16>;
762def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx,
763                          v4i32, v8i16>;
764def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb,
765                          v8i16, v16i8>;
766def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh,
767                          v4i32, v8i16>;
768
769
770// Altivec Comparisons.
771
772class VCMP<bits<10> xo, string asmstr, ValueType Ty>
773  : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
774              IIC_VecFPCompare,
775              [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>;
776class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
777  : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
778              IIC_VecFPCompare,
779              [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> {
780  let Defs = [CR6];
781  let RC = 1;
782}
783
784// f32 element comparisons.0
785def VCMPBFP   : VCMP <966, "vcmpbfp $vD, $vA, $vB"  , v4f32>;
786def VCMPBFPo  : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
787def VCMPEQFP  : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
788def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
789def VCMPGEFP  : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
790def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
791def VCMPGTFP  : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
792def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
793
794// i8 element comparisons.
795def VCMPEQUB  : VCMP <  6, "vcmpequb $vD, $vA, $vB" , v16i8>;
796def VCMPEQUBo : VCMPo<  6, "vcmpequb. $vD, $vA, $vB", v16i8>;
797def VCMPGTSB  : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
798def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
799def VCMPGTUB  : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
800def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
801
802// i16 element comparisons.
803def VCMPEQUH  : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
804def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
805def VCMPGTSH  : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
806def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
807def VCMPGTUH  : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
808def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
809
810// i32 element comparisons.
811def VCMPEQUW  : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
812def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
813def VCMPGTSW  : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
814def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
815def VCMPGTUW  : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
816def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
817
818let isCodeGenOnly = 1 in {
819def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
820                      "vxor $vD, $vD, $vD", IIC_VecFP,
821                      [(set v16i8:$vD, (v16i8 immAllZerosV))]>;
822def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
823                      "vxor $vD, $vD, $vD", IIC_VecFP,
824                      [(set v8i16:$vD, (v8i16 immAllZerosV))]>;
825def V_SET0  : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
826                      "vxor $vD, $vD, $vD", IIC_VecFP,
827                      [(set v4i32:$vD, (v4i32 immAllZerosV))]>;
828
829let IMM=-1 in {
830def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins),
831                      "vspltisw $vD, -1", IIC_VecFP,
832                      [(set v16i8:$vD, (v16i8 immAllOnesV))]>;
833def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins),
834                      "vspltisw $vD, -1", IIC_VecFP,
835                      [(set v8i16:$vD, (v8i16 immAllOnesV))]>;
836def V_SETALLONES  : VXForm_3<908, (outs vrrc:$vD), (ins),
837                      "vspltisw $vD, -1", IIC_VecFP,
838                      [(set v4i32:$vD, (v4i32 immAllOnesV))]>;
839}
840}
841} // VALU Operations.
842
843//===----------------------------------------------------------------------===//
844// Additional Altivec Patterns
845//
846
847// Loads.
848def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;
849
850// Stores.
851def : Pat<(store v4i32:$rS, xoaddr:$dst),
852          (STVX $rS, xoaddr:$dst)>;
853
854// Bit conversions.
855def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
856def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
857def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
858def : Pat<(v16i8 (bitconvert (v2i64 VRRC:$src))), (v16i8 VRRC:$src)>;
859def : Pat<(v16i8 (bitconvert (v1i128 VRRC:$src))), (v16i8 VRRC:$src)>;
860
861def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
862def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
863def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
864def : Pat<(v8i16 (bitconvert (v2i64 VRRC:$src))), (v8i16 VRRC:$src)>;
865def : Pat<(v8i16 (bitconvert (v1i128 VRRC:$src))), (v8i16 VRRC:$src)>;
866
867def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
868def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
869def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
870def : Pat<(v4i32 (bitconvert (v2i64 VRRC:$src))), (v4i32 VRRC:$src)>;
871def : Pat<(v4i32 (bitconvert (v1i128 VRRC:$src))), (v4i32 VRRC:$src)>;
872
873def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
874def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
875def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
876def : Pat<(v4f32 (bitconvert (v2i64 VRRC:$src))), (v4f32 VRRC:$src)>;
877def : Pat<(v4f32 (bitconvert (v1i128 VRRC:$src))), (v4f32 VRRC:$src)>;
878
879def : Pat<(v2i64 (bitconvert (v16i8 VRRC:$src))), (v2i64 VRRC:$src)>;
880def : Pat<(v2i64 (bitconvert (v8i16 VRRC:$src))), (v2i64 VRRC:$src)>;
881def : Pat<(v2i64 (bitconvert (v4i32 VRRC:$src))), (v2i64 VRRC:$src)>;
882def : Pat<(v2i64 (bitconvert (v4f32 VRRC:$src))), (v2i64 VRRC:$src)>;
883def : Pat<(v2i64 (bitconvert (v1i128 VRRC:$src))), (v2i64 VRRC:$src)>;
884
885def : Pat<(v1i128 (bitconvert (v16i8 VRRC:$src))), (v1i128 VRRC:$src)>;
886def : Pat<(v1i128 (bitconvert (v8i16 VRRC:$src))), (v1i128 VRRC:$src)>;
887def : Pat<(v1i128 (bitconvert (v4i32 VRRC:$src))), (v1i128 VRRC:$src)>;
888def : Pat<(v1i128 (bitconvert (v4f32 VRRC:$src))), (v1i128 VRRC:$src)>;
889def : Pat<(v1i128 (bitconvert (v2i64 VRRC:$src))), (v1i128 VRRC:$src)>;
890
891// Shuffles.
892
893// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x)
894def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef),
895        (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>;
896def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef),
897        (VPKUWUM $vA, $vA)>;
898def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef),
899        (VPKUHUM $vA, $vA)>;
900
901// Match vsldoi(y,x), vpkuwum(y,x), vpkuhum(y,x), i.e., swapped operands.
902// These fragments are matched for little-endian, where the inputs must
903// be swapped for correct semantics.
904def:Pat<(vsldoi_swapped_shuffle:$in v16i8:$vA, v16i8:$vB),
905        (VSLDOI $vB, $vA, (VSLDOI_swapped_get_imm $in))>;
906def:Pat<(vpkuwum_swapped_shuffle v16i8:$vA, v16i8:$vB),
907        (VPKUWUM $vB, $vA)>;
908def:Pat<(vpkuhum_swapped_shuffle v16i8:$vA, v16i8:$vB),
909        (VPKUHUM $vB, $vA)>;
910
911// Match vmrg*(x,x)
912def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef),
913        (VMRGLB $vA, $vA)>;
914def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef),
915        (VMRGLH $vA, $vA)>;
916def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef),
917        (VMRGLW $vA, $vA)>;
918def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef),
919        (VMRGHB $vA, $vA)>;
920def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef),
921        (VMRGHH $vA, $vA)>;
922def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef),
923        (VMRGHW $vA, $vA)>;
924
925// Match vmrg*(y,x), i.e., swapped operands.  These fragments
926// are matched for little-endian, where the inputs must be
927// swapped for correct semantics.
928def:Pat<(vmrglb_swapped_shuffle v16i8:$vA, v16i8:$vB),
929        (VMRGLB $vB, $vA)>;
930def:Pat<(vmrglh_swapped_shuffle v16i8:$vA, v16i8:$vB),
931        (VMRGLH $vB, $vA)>;
932def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB),
933        (VMRGLW $vB, $vA)>;
934def:Pat<(vmrghb_swapped_shuffle v16i8:$vA, v16i8:$vB),
935        (VMRGHB $vB, $vA)>;
936def:Pat<(vmrghh_swapped_shuffle v16i8:$vA, v16i8:$vB),
937        (VMRGHH $vB, $vA)>;
938def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB),
939        (VMRGHW $vB, $vA)>;
940
941// Logical Operations
942def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>;
943
944def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)),
945          (VNOR $A, $B)>;
946def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)),
947          (VANDC $A, $B)>;
948
949def : Pat<(fmul v4f32:$vA, v4f32:$vB),
950          (VMADDFP $vA, $vB,
951             (v4i32 (VSLW (V_SETALLONES), (V_SETALLONES))))>;
952
953// Fused multiply add and multiply sub for packed float.  These are represented
954// separately from the real instructions above, for operations that must have
955// the additional precision, such as Newton-Rhapson (used by divide, sqrt)
956def : Pat<(PPCvmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
957          (VMADDFP $A, $B, $C)>;
958def : Pat<(PPCvnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
959          (VNMSUBFP $A, $B, $C)>;
960
961def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
962          (VMADDFP $A, $B, $C)>;
963def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
964          (VNMSUBFP $A, $B, $C)>;
965
966def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC),
967          (VPERM $vA, $vB, $vC)>;
968
969def : Pat<(PPCfre v4f32:$A), (VREFP $A)>;
970def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>;
971
972// Vector shifts
973def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)),
974          (v16i8 (VSLB $vA, $vB))>;
975def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)),
976          (v8i16 (VSLH $vA, $vB))>;
977def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)),
978          (v4i32 (VSLW $vA, $vB))>;
979
980def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)),
981          (v16i8 (VSRB $vA, $vB))>;
982def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)),
983          (v8i16 (VSRH $vA, $vB))>;
984def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)),
985          (v4i32 (VSRW $vA, $vB))>;
986
987def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)),
988          (v16i8 (VSRAB $vA, $vB))>;
989def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)),
990          (v8i16 (VSRAH $vA, $vB))>;
991def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)),
992          (v4i32 (VSRAW $vA, $vB))>;
993
994// Float to integer and integer to float conversions
995def : Pat<(v4i32 (fp_to_sint v4f32:$vA)),
996           (VCTSXS_0 $vA)>;
997def : Pat<(v4i32 (fp_to_uint v4f32:$vA)),
998           (VCTUXS_0 $vA)>;
999def : Pat<(v4f32 (sint_to_fp v4i32:$vA)),
1000           (VCFSX_0 $vA)>;
1001def : Pat<(v4f32 (uint_to_fp v4i32:$vA)),
1002           (VCFUX_0 $vA)>;
1003
1004// Floating-point rounding
1005def : Pat<(v4f32 (ffloor v4f32:$vA)),
1006          (VRFIM $vA)>;
1007def : Pat<(v4f32 (fceil v4f32:$vA)),
1008          (VRFIP $vA)>;
1009def : Pat<(v4f32 (ftrunc v4f32:$vA)),
1010          (VRFIZ $vA)>;
1011def : Pat<(v4f32 (fnearbyint v4f32:$vA)),
1012          (VRFIN $vA)>;
1013
1014} // end HasAltivec
1015
1016def HasP8Altivec : Predicate<"PPCSubTarget->hasP8Altivec()">;
1017def HasP8Crypto : Predicate<"PPCSubTarget->hasP8Crypto()">;
1018let Predicates = [HasP8Altivec] in {
1019
1020let isCommutable = 1 in {
1021def VMULESW : VX1_Int_Ty2<904, "vmulesw", int_ppc_altivec_vmulesw,
1022                          v2i64, v4i32>;
1023def VMULEUW : VX1_Int_Ty2<648, "vmuleuw", int_ppc_altivec_vmuleuw,
1024                          v2i64, v4i32>;
1025def VMULOSW : VX1_Int_Ty2<392, "vmulosw", int_ppc_altivec_vmulosw,
1026                          v2i64, v4i32>;
1027def VMULOUW : VX1_Int_Ty2<136, "vmulouw", int_ppc_altivec_vmulouw,
1028                          v2i64, v4i32>;
1029def VMULUWM : VXForm_1<137, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1030                       "vmuluwm $vD, $vA, $vB", IIC_VecGeneral,
1031                       [(set v4i32:$vD, (mul v4i32:$vA, v4i32:$vB))]>;
1032def VMAXSD : VX1_Int_Ty<450, "vmaxsd", int_ppc_altivec_vmaxsd, v2i64>;
1033def VMAXUD : VX1_Int_Ty<194, "vmaxud", int_ppc_altivec_vmaxud, v2i64>;
1034def VMINSD : VX1_Int_Ty<962, "vminsd", int_ppc_altivec_vminsd, v2i64>;
1035def VMINUD : VX1_Int_Ty<706, "vminud", int_ppc_altivec_vminud, v2i64>;
1036} // isCommutable
1037
1038// Vector merge
1039def VMRGEW : VXForm_1<1932, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1040                      "vmrgew $vD, $vA, $vB", IIC_VecFP,
1041                      [(set v16i8:$vD, (vmrgew_shuffle v16i8:$vA, v16i8:$vB))]>;
1042def VMRGOW : VXForm_1<1676, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1043                      "vmrgow $vD, $vA, $vB", IIC_VecFP,
1044                      [(set v16i8:$vD, (vmrgow_shuffle v16i8:$vA, v16i8:$vB))]>;
1045
1046// Match vmrgew(x,x) and vmrgow(x,x)
1047def:Pat<(vmrgew_unary_shuffle v16i8:$vA, undef),
1048        (VMRGEW $vA, $vA)>;
1049def:Pat<(vmrgow_unary_shuffle v16i8:$vA, undef),
1050        (VMRGOW $vA, $vA)>;
1051
1052// Match vmrgew(y,x) and vmrgow(y,x), i.e., swapped operands.  These fragments
1053// are matched for little-endian, where the inputs must be swapped for correct
1054// semantics.w
1055def:Pat<(vmrgew_swapped_shuffle v16i8:$vA, v16i8:$vB),
1056        (VMRGEW $vB, $vA)>;
1057def:Pat<(vmrgow_swapped_shuffle v16i8:$vA, v16i8:$vB),
1058        (VMRGOW $vB, $vA)>;
1059
1060
1061// Vector shifts
1062def VRLD : VX1_Int_Ty<196, "vrld", int_ppc_altivec_vrld, v2i64>;
1063def VSLD : VXForm_1<1476, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1064                    "vsld $vD, $vA, $vB", IIC_VecGeneral,
1065                    [(set v2i64:$vD, (shl v2i64:$vA, v2i64:$vB))]>;
1066def VSRD : VXForm_1<1732, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1067                   "vsrd $vD, $vA, $vB", IIC_VecGeneral,
1068                   [(set v2i64:$vD, (srl v2i64:$vA, v2i64:$vB))]>;
1069def VSRAD : VXForm_1<964, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1070                    "vsrad $vD, $vA, $vB", IIC_VecGeneral,
1071                    [(set v2i64:$vD, (sra v2i64:$vA, v2i64:$vB))]>;
1072
1073// Vector Integer Arithmetic Instructions
1074let isCommutable = 1 in {
1075def VADDUDM : VXForm_1<192, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1076                       "vaddudm $vD, $vA, $vB", IIC_VecGeneral,
1077                       [(set v2i64:$vD, (add v2i64:$vA, v2i64:$vB))]>;
1078def VADDUQM : VXForm_1<256, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1079                       "vadduqm $vD, $vA, $vB", IIC_VecGeneral,
1080                       [(set v1i128:$vD, (add v1i128:$vA, v1i128:$vB))]>;
1081} // isCommutable
1082
1083// Vector Quadword Add
1084def VADDEUQM : VA1a_Int_Ty<60, "vaddeuqm", int_ppc_altivec_vaddeuqm, v1i128>;
1085def VADDCUQ  : VX1_Int_Ty<320, "vaddcuq", int_ppc_altivec_vaddcuq, v1i128>;
1086def VADDECUQ : VA1a_Int_Ty<61, "vaddecuq", int_ppc_altivec_vaddecuq, v1i128>;
1087
1088// Vector Doubleword Subtract
1089def VSUBUDM : VXForm_1<1216, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1090                       "vsubudm $vD, $vA, $vB", IIC_VecGeneral,
1091                       [(set v2i64:$vD, (sub v2i64:$vA, v2i64:$vB))]>;
1092
1093// Vector Quadword Subtract
1094def VSUBUQM : VXForm_1<1280, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1095                       "vsubuqm $vD, $vA, $vB", IIC_VecGeneral,
1096                       [(set v1i128:$vD, (sub v1i128:$vA, v1i128:$vB))]>;
1097def VSUBEUQM : VA1a_Int_Ty<62, "vsubeuqm", int_ppc_altivec_vsubeuqm, v1i128>;
1098def VSUBCUQ  : VX1_Int_Ty<1344, "vsubcuq", int_ppc_altivec_vsubcuq, v1i128>;
1099def VSUBECUQ : VA1a_Int_Ty<63, "vsubecuq", int_ppc_altivec_vsubecuq, v1i128>;
1100
1101// Count Leading Zeros
1102def VCLZB : VXForm_2<1794, (outs vrrc:$vD), (ins vrrc:$vB),
1103                     "vclzb $vD, $vB", IIC_VecGeneral,
1104                     [(set v16i8:$vD, (ctlz v16i8:$vB))]>;
1105def VCLZH : VXForm_2<1858, (outs vrrc:$vD), (ins vrrc:$vB),
1106                     "vclzh $vD, $vB", IIC_VecGeneral,
1107                     [(set v8i16:$vD, (ctlz v8i16:$vB))]>;
1108def VCLZW : VXForm_2<1922, (outs vrrc:$vD), (ins vrrc:$vB),
1109                     "vclzw $vD, $vB", IIC_VecGeneral,
1110                     [(set v4i32:$vD, (ctlz v4i32:$vB))]>;
1111def VCLZD : VXForm_2<1986, (outs vrrc:$vD), (ins vrrc:$vB),
1112                     "vclzd $vD, $vB", IIC_VecGeneral,
1113                     [(set v2i64:$vD, (ctlz v2i64:$vB))]>;
1114
1115// Population Count
1116def VPOPCNTB : VXForm_2<1795, (outs vrrc:$vD), (ins vrrc:$vB),
1117                        "vpopcntb $vD, $vB", IIC_VecGeneral,
1118                        [(set v16i8:$vD, (ctpop v16i8:$vB))]>;
1119def VPOPCNTH : VXForm_2<1859, (outs vrrc:$vD), (ins vrrc:$vB),
1120                        "vpopcnth $vD, $vB", IIC_VecGeneral,
1121                        [(set v8i16:$vD, (ctpop v8i16:$vB))]>;
1122def VPOPCNTW : VXForm_2<1923, (outs vrrc:$vD), (ins vrrc:$vB),
1123                        "vpopcntw $vD, $vB", IIC_VecGeneral,
1124                        [(set v4i32:$vD, (ctpop v4i32:$vB))]>;
1125def VPOPCNTD : VXForm_2<1987, (outs vrrc:$vD), (ins vrrc:$vB),
1126                        "vpopcntd $vD, $vB", IIC_VecGeneral,
1127                        [(set v2i64:$vD, (ctpop v2i64:$vB))]>;
1128
1129let isCommutable = 1 in {
1130// FIXME: Use AddedComplexity > 400 to ensure these patterns match before the
1131//        VSX equivalents. We need to fix this up at some point. Two possible
1132//        solutions for this problem:
1133//        1. Disable Altivec patterns that compete with VSX patterns using the
1134//           !HasVSX predicate. This essentially favours VSX over Altivec, in
1135//           hopes of reducing register pressure (larger register set using VSX
1136//           instructions than VMX instructions)
1137//        2. Employ a more disciplined use of AddedComplexity, which would provide
1138//           more fine-grained control than option 1. This would be beneficial
1139//           if we find situations where Altivec is really preferred over VSX.
1140def VEQV  : VXForm_1<1668, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1141                     "veqv $vD, $vA, $vB", IIC_VecGeneral,
1142                     [(set v4i32:$vD, (vnot_ppc (xor v4i32:$vA, v4i32:$vB)))]>;
1143def VNAND : VXForm_1<1412, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1144                     "vnand $vD, $vA, $vB", IIC_VecGeneral,
1145                     [(set v4i32:$vD, (vnot_ppc (and v4i32:$vA, v4i32:$vB)))]>;
1146} // isCommutable
1147
1148def VORC : VXForm_1<1348, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1149                      "vorc $vD, $vA, $vB", IIC_VecGeneral,
1150                      [(set v4i32:$vD, (or v4i32:$vA,
1151                                           (vnot_ppc v4i32:$vB)))]>;
1152
1153// i64 element comparisons.
1154def VCMPEQUD  : VCMP <199, "vcmpequd $vD, $vA, $vB" , v2i64>;
1155def VCMPEQUDo : VCMPo<199, "vcmpequd. $vD, $vA, $vB", v2i64>;
1156def VCMPGTSD  : VCMP <967, "vcmpgtsd $vD, $vA, $vB" , v2i64>;
1157def VCMPGTSDo : VCMPo<967, "vcmpgtsd. $vD, $vA, $vB", v2i64>;
1158def VCMPGTUD  : VCMP <711, "vcmpgtud $vD, $vA, $vB" , v2i64>;
1159def VCMPGTUDo : VCMPo<711, "vcmpgtud. $vD, $vA, $vB", v2i64>;
1160
1161// The cryptography instructions that do not require Category:Vector.Crypto
1162def VPMSUMB : VX1_Int_Ty<1032, "vpmsumb",
1163                         int_ppc_altivec_crypto_vpmsumb, v16i8>;
1164def VPMSUMH : VX1_Int_Ty<1096, "vpmsumh",
1165                         int_ppc_altivec_crypto_vpmsumh, v8i16>;
1166def VPMSUMW : VX1_Int_Ty<1160, "vpmsumw",
1167                         int_ppc_altivec_crypto_vpmsumw, v4i32>;
1168def VPMSUMD : VX1_Int_Ty<1224, "vpmsumd",
1169                         int_ppc_altivec_crypto_vpmsumd, v2i64>;
1170def VPERMXOR : VA1a_Int_Ty<45, "vpermxor",
1171                         int_ppc_altivec_crypto_vpermxor, v16i8>;
1172
1173// Vector doubleword integer pack and unpack.
1174def VPKSDSS : VX1_Int_Ty2<1486, "vpksdss", int_ppc_altivec_vpksdss,
1175                          v4i32, v2i64>;
1176def VPKSDUS : VX1_Int_Ty2<1358, "vpksdus", int_ppc_altivec_vpksdus,
1177                          v4i32, v2i64>;
1178def VPKUDUM : VXForm_1<1102, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1179                       "vpkudum $vD, $vA, $vB", IIC_VecFP,
1180                       [(set v16i8:$vD,
1181                         (vpkudum_shuffle v16i8:$vA, v16i8:$vB))]>;
1182def VPKUDUS : VX1_Int_Ty2<1230, "vpkudus", int_ppc_altivec_vpkudus,
1183                          v4i32, v2i64>;
1184def VUPKHSW : VX2_Int_Ty2<1614, "vupkhsw", int_ppc_altivec_vupkhsw,
1185                          v2i64, v4i32>;
1186def VUPKLSW : VX2_Int_Ty2<1742, "vupklsw", int_ppc_altivec_vupklsw,
1187                          v2i64, v4i32>;
1188
1189// Shuffle patterns for unary and swapped (LE) vector pack modulo.
1190def:Pat<(vpkudum_unary_shuffle v16i8:$vA, undef),
1191        (VPKUDUM $vA, $vA)>;
1192def:Pat<(vpkudum_swapped_shuffle v16i8:$vA, v16i8:$vB),
1193        (VPKUDUM $vB, $vA)>;
1194
1195def VGBBD : VX2_Int_Ty2<1292, "vgbbd", int_ppc_altivec_vgbbd, v16i8, v16i8>;
1196def VBPERMQ : VX1_Int_Ty2<1356, "vbpermq", int_ppc_altivec_vbpermq,
1197                          v2i64, v16i8>;
1198} // end HasP8Altivec
1199
1200// Crypto instructions (from builtins)
1201let Predicates = [HasP8Crypto] in {
1202def VSHASIGMAW : VXCR_Int_Ty<1666, "vshasigmaw",
1203                              int_ppc_altivec_crypto_vshasigmaw, v4i32>;
1204def VSHASIGMAD : VXCR_Int_Ty<1730, "vshasigmad",
1205                              int_ppc_altivec_crypto_vshasigmad, v2i64>;
1206def VCIPHER : VX1_Int_Ty<1288, "vcipher", int_ppc_altivec_crypto_vcipher,
1207                         v2i64>;
1208def VCIPHERLAST : VX1_Int_Ty<1289, "vcipherlast",
1209                              int_ppc_altivec_crypto_vcipherlast, v2i64>;
1210def VNCIPHER : VX1_Int_Ty<1352, "vncipher",
1211                          int_ppc_altivec_crypto_vncipher, v2i64>;
1212def VNCIPHERLAST : VX1_Int_Ty<1353, "vncipherlast",
1213                              int_ppc_altivec_crypto_vncipherlast, v2i64>;
1214def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>;
1215} // HasP8Crypto
1216
1217// The following altivec instructions were introduced in Power ISA 3.0
1218def HasP9Altivec : Predicate<"PPCSubTarget->hasP9Altivec()">;
1219let Predicates = [HasP9Altivec] in {
1220
1221// Vector Compare Not Equal (Zero)
1222class P9VCMP<bits<10> xo, string asmstr, ValueType Ty>
1223  : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
1224              IIC_VecFPCompare, []>;
1225class P9VCMPo<bits<10> xo, string asmstr, ValueType Ty>
1226  : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
1227              IIC_VecFPCompare, []> {
1228  let Defs = [CR6];
1229  let RC = 1;
1230}
1231
1232// i8 element comparisons.
1233def VCMPNEB   : P9VCMP <  7, "vcmpneb $vD, $vA, $vB"  , v16i8>;
1234def VCMPNEBo  : P9VCMPo<  7, "vcmpneb. $vD, $vA, $vB" , v16i8>;
1235def VCMPNEZB  : P9VCMP <263, "vcmpnezb $vD, $vA, $vB" , v16i8>;
1236def VCMPNEZBo : P9VCMPo<263, "vcmpnezb. $vD, $vA, $vB", v16i8>;
1237
1238// i16 element comparisons.
1239def VCMPNEH   : P9VCMP < 71, "vcmpneh $vD, $vA, $vB"  , v8i16>;
1240def VCMPNEHo  : P9VCMPo< 71, "vcmpneh. $vD, $vA, $vB" , v8i16>;
1241def VCMPNEZH  : P9VCMP <327, "vcmpnezh $vD, $vA, $vB" , v8i16>;
1242def VCMPNEZHo : P9VCMPo<327, "vcmpnezh. $vD, $vA, $vB", v8i16>;
1243
1244// i32 element comparisons.
1245def VCMPNEW   : P9VCMP <135, "vcmpnew $vD, $vA, $vB"  , v4i32>;
1246def VCMPNEWo  : P9VCMPo<135, "vcmpnew. $vD, $vA, $vB" , v4i32>;
1247def VCMPNEZW  : P9VCMP <391, "vcmpnezw $vD, $vA, $vB" , v4i32>;
1248def VCMPNEZWo : P9VCMPo<391, "vcmpnezw. $vD, $vA, $vB", v4i32>;
1249
1250// VX-Form: [PO VRT / UIM VRB XO].
1251// We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent
1252// "/ UIM" (1 + 4 bit)
1253class VX1_VT5_UIM5_VB5<bits<11> xo, string opc, list<dag> pattern>
1254  : VXForm_1<xo, (outs vrrc:$vD), (ins u4imm:$UIMM, vrrc:$vB),
1255             !strconcat(opc, " $vD, $vB, $UIMM"), IIC_VecGeneral, pattern>;
1256
1257class VX1_RT5_RA5_VB5<bits<11> xo, string opc, list<dag> pattern>
1258  : VXForm_1<xo, (outs g8rc:$rD), (ins g8rc:$rA, vrrc:$vB),
1259             !strconcat(opc, " $rD, $rA, $vB"), IIC_VecGeneral, pattern>;
1260
1261// Vector Extract Unsigned
1262def VEXTRACTUB : VX1_VT5_UIM5_VB5<525, "vextractub", []>;
1263def VEXTRACTUH : VX1_VT5_UIM5_VB5<589, "vextractuh", []>;
1264def VEXTRACTUW : VX1_VT5_UIM5_VB5<653, "vextractuw", []>;
1265def VEXTRACTD  : VX1_VT5_UIM5_VB5<717, "vextractd" , []>;
1266
1267// Vector Extract Unsigned Byte/Halfword/Word Left/Right-Indexed
1268def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>;
1269def VEXTUBRX : VX1_RT5_RA5_VB5<1805, "vextubrx", []>;
1270def VEXTUHLX : VX1_RT5_RA5_VB5<1613, "vextuhlx", []>;
1271def VEXTUHRX : VX1_RT5_RA5_VB5<1869, "vextuhrx", []>;
1272def VEXTUWLX : VX1_RT5_RA5_VB5<1677, "vextuwlx", []>;
1273def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>;
1274
1275// Vector Insert Element Instructions
1276def VINSERTB : VX1_VT5_UIM5_VB5<781, "vinsertb", []>;
1277def VINSERTH : VX1_VT5_UIM5_VB5<845, "vinserth", []>;
1278def VINSERTW : VX1_VT5_UIM5_VB5<909, "vinsertw", []>;
1279def VINSERTD : VX1_VT5_UIM5_VB5<973, "vinsertd", []>;
1280
1281class VX_VT5_EO5_VB5<bits<11> xo, bits<5> eo, string opc, list<dag> pattern>
1282  : VXForm_RD5_XO5_RS5<xo, eo, (outs vrrc:$vD), (ins vrrc:$vB),
1283                       !strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>;
1284
1285// Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[rD]
1286def VCLZLSBB : VXForm_RD5_XO5_RS5<1538, 0, (outs g8rc:$rD), (ins vrrc:$vB),
1287                                  "vclzlsbb $rD, $vB", IIC_VecGeneral, []>;
1288def VCTZLSBB : VXForm_RD5_XO5_RS5<1538, 1, (outs g8rc:$rD), (ins vrrc:$vB),
1289                                  "vctzlsbb $rD, $vB", IIC_VecGeneral, []>;
1290// Vector Count Trailing Zeros
1291def VCTZB : VX_VT5_EO5_VB5<1538, 28, "vctzb", []>;
1292def VCTZH : VX_VT5_EO5_VB5<1538, 29, "vctzh", []>;
1293def VCTZW : VX_VT5_EO5_VB5<1538, 30, "vctzw", []>;
1294def VCTZD : VX_VT5_EO5_VB5<1538, 31, "vctzd", []>;
1295
1296// Vector Extend Sign
1297def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w", []>;
1298def VEXTSH2W : VX_VT5_EO5_VB5<1538, 17, "vextsh2w", []>;
1299def VEXTSB2D : VX_VT5_EO5_VB5<1538, 24, "vextsb2d", []>;
1300def VEXTSH2D : VX_VT5_EO5_VB5<1538, 25, "vextsh2d", []>;
1301def VEXTSW2D : VX_VT5_EO5_VB5<1538, 26, "vextsw2d", []>;
1302
1303// Vector Integer Negate
1304def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw", []>;
1305def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd", []>;
1306
1307// Vector Parity Byte
1308def VPRTYBW : VX_VT5_EO5_VB5<1538,  8, "vprtybw", []>;
1309def VPRTYBD : VX_VT5_EO5_VB5<1538,  9, "vprtybd", []>;
1310def VPRTYBQ : VX_VT5_EO5_VB5<1538, 10, "vprtybq", []>;
1311
1312// Vector (Bit) Permute (Right-indexed)
1313def VBPERMD : VXForm_1<1484, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1314                       "vbpermd $vD, $vA, $vB", IIC_VecFP, []>;
1315def VPERMR : VAForm_1a<59, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
1316                       "vpermr $vD, $vA, $vB, $vC", IIC_VecFP, []>;
1317
1318class VX1_VT5_VA5_VB5<bits<11> xo, string opc, list<dag> pattern>
1319  : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1320             !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern>;
1321
1322// Vector Rotate Left Mask/Mask-Insert
1323def VRLWNM : VX1_VT5_VA5_VB5<389, "vrlwnm", []>;
1324def VRLWMI : VX1_VT5_VA5_VB5<133, "vrlwmi", []>;
1325def VRLDNM : VX1_VT5_VA5_VB5<453, "vrldnm", []>;
1326def VRLDMI : VX1_VT5_VA5_VB5<197, "vrldmi", []>;
1327
1328// Vector Shift Left/Right
1329def VSLV : VX1_VT5_VA5_VB5<1860, "vslv", []>;
1330def VSRV : VX1_VT5_VA5_VB5<1796, "vsrv", []>;
1331
1332// Vector Multiply-by-10 (& Write Carry) Unsigned Quadword
1333def VMUL10UQ   : VXForm_BX<513, (outs vrrc:$vD), (ins vrrc:$vA),
1334                           "vmul10uq $vD, $vA", IIC_VecFP, []>;
1335def VMUL10CUQ  : VXForm_BX<  1, (outs vrrc:$vD), (ins vrrc:$vA),
1336                           "vmul10cuq $vD, $vA", IIC_VecFP, []>;
1337
1338// Vector Multiply-by-10 Extended (& Write Carry) Unsigned Quadword
1339def VMUL10EUQ  : VX1_VT5_VA5_VB5<577, "vmul10euq" , []>;
1340def VMUL10ECUQ : VX1_VT5_VA5_VB5< 65, "vmul10ecuq", []>;
1341
1342// Decimal Integer Format Conversion Instructions
1343
1344// [PO VRT EO VRB 1 PS XO], "_o" means CR6 is set.
1345class VX_VT5_EO5_VB5_PS1_XO9_o<bits<5> eo, bits<9> xo, string opc,
1346                               list<dag> pattern>
1347  : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB, u1imm:$PS),
1348                        !strconcat(opc, " $vD, $vB, $PS"), IIC_VecFP, pattern> {
1349  let Defs = [CR6];
1350}
1351
1352// [PO VRT EO VRB 1 / XO]
1353class VX_VT5_EO5_VB5_XO9_o<bits<5> eo, bits<9> xo, string opc,
1354                           list<dag> pattern>
1355  : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB),
1356                           !strconcat(opc, " $vD, $vB"), IIC_VecFP, pattern> {
1357  let Defs = [CR6];
1358  let PS = 0;
1359}
1360
1361// Decimal Convert From/to National/Zoned/Signed-QWord
1362def BCDCFNo  : VX_VT5_EO5_VB5_PS1_XO9_o<7, 385, "bcdcfn." , []>;
1363def BCDCFZo  : VX_VT5_EO5_VB5_PS1_XO9_o<6, 385, "bcdcfz." , []>;
1364def BCDCTNo  : VX_VT5_EO5_VB5_XO9_o    <5, 385, "bcdctn." , []>;
1365def BCDCTZo  : VX_VT5_EO5_VB5_PS1_XO9_o<4, 385, "bcdctz." , []>;
1366def BCDCFSQo : VX_VT5_EO5_VB5_PS1_XO9_o<2, 385, "bcdcfsq.", []>;
1367def BCDCTSQo : VX_VT5_EO5_VB5_XO9_o    <0, 385, "bcdctsq.", []>;
1368
1369// Decimal Copy-Sign/Set-Sign
1370let Defs = [CR6] in
1371def BCDCPSGNo : VX1_VT5_VA5_VB5<833, "bcdcpsgn.", []>;
1372
1373def BCDSETSGNo : VX_VT5_EO5_VB5_PS1_XO9_o<31, 385, "bcdsetsgn.", []>;
1374
1375// [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is set.
1376class VX_VT5_VA5_VB5_PS1_XO9_o<bits<9> xo, string opc, list<dag> pattern>
1377  : VX_RD5_RSp5_PS1_XO9<xo,
1378                   (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u1imm:$PS),
1379                   !strconcat(opc, " $vD, $vA, $vB, $PS"), IIC_VecFP, pattern> {
1380  let Defs = [CR6];
1381}
1382
1383// [PO VRT VRA VRB 1 / XO]
1384class VX_VT5_VA5_VB5_XO9_o<bits<9> xo, string opc, list<dag> pattern>
1385  : VX_RD5_RSp5_PS1_XO9<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1386                        !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern> {
1387  let Defs = [CR6];
1388  let PS = 0;
1389}
1390
1391// Decimal Shift/Unsigned-Shift/Shift-and-Round
1392def BCDSo :  VX_VT5_VA5_VB5_PS1_XO9_o<193, "bcds." , []>;
1393def BCDUSo : VX_VT5_VA5_VB5_XO9_o    <129, "bcdus.", []>;
1394def BCDSRo : VX_VT5_VA5_VB5_PS1_XO9_o<449, "bcdsr.", []>;
1395
1396// Decimal (Unsigned) Truncate
1397def BCDTRUNCo :  VX_VT5_VA5_VB5_PS1_XO9_o<257, "bcdtrunc." , []>;
1398def BCDUTRUNCo : VX_VT5_VA5_VB5_XO9_o    <321, "bcdutrunc.", []>;
1399} // end HasP9Altivec
1400